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target/mips: Reduce CPUState scope when used with CPU_FOREACH()

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When possible, reduce CPUState variable scope.
Prefer cpu_env(cpu) over &cpu->env.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-8-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2026-05-06 14:37:24 +02:00
parent ea6904ce60
commit 734bd83030
3 changed files with 25 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
target/mips/internal.h
View File

@@ -280,7 +280,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
static inline int mips_vp_active(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
CPUState *cs = first_cpu;
/* Check if the VP disabled other VPs (which means the VP is enabled) */
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
@@ -288,10 +288,11 @@ static inline int mips_vp_active(CPUMIPSState *env)
}
/* Check if the virtual processor is disabled due to a DVP */
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
if ((&other_cpu->env != env) &&
((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
CPU_FOREACH(cs) {
CPUMIPSState *other_env = cpu_env(cs);
if ((other_env != env) &&
((other_env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
return 0;
}
}

28
target/mips/tcg/system/cp0_helper.c
View File

@@ -1566,13 +1566,14 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
MIPSCPU *cpu = env_archcpu(env);
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
CPUState *cs = first_cpu;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
@@ -1585,13 +1586,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
target_ulong helper_evpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
MIPSCPU *cpu = env_archcpu(env);
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
CPUState *cs = first_cpu;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
if (&other_cpu->env != env
/* If the VPE is WFI, don't disturb its sleep. */
@@ -1608,12 +1610,13 @@ target_ulong helper_evpe(CPUMIPSState *env)
/* R6 Multi-threading */
target_ulong helper_dvp(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->CP0_VPControl;
if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
CPUState *cpu = first_cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);
/* Turn off all VPs except the one executing the dvp. */
if (&other_cpu->env != env) {
mips_vpe_sleep(other_cpu);
@@ -1626,12 +1629,13 @@ target_ulong helper_dvp(CPUMIPSState *env)
target_ulong helper_evp(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->CP0_VPControl;
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
CPUState *cpu = first_cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);
if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
/*
* If the VP is WFI, don't disturb its sleep.

7
target/mips/tcg/system/tlb_helper.c
View File

@@ -346,15 +346,14 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
uint8_t invMsgR = 0;
uint32_t invMsgMMid = env->CP0_MemoryMapID;
CPUState *other_cs = first_cpu;
CPUState *cpu = first_cpu;
#ifdef TARGET_MIPS64
invMsgR = extract64(arg, 62, 2);
#endif
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,
CPU_FOREACH(cpu) {
global_invalidate_tlb(cpu_env(cpu), invMsgVPN2, invMsgR, invMsgMMid,
invAll, invVAMMid, invMMid, invVA);
}
}