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hw/core/machine: topology functions capabilities added

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Add two functions one of which finds the lowest cache level defined in
the cache description input, and the other checks if a given cache
topology is defined at a particular cache level

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20260311160609.358-3-alireza.sanaee@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alireza Sanaee
2026-04-23 10:24:09 +01:00
committed by Peter Maydell
parent 0dc85587be
commit 8d53896b44
2 changed files with 57 additions and 0 deletions
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52
hw/core/machine-smp.c
View File

@@ -406,3 +406,55 @@ bool machine_check_smp_cache(const MachineState *ms, Error **errp)
return true;
}
/*
* This function assumes L3 and L2 have unified cache and L1 is split L1d and
* L1i.
*/
bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
int *lowest_cache_level,
CpuTopologyLevel topo_level)
{
enum CacheLevelAndType cache_level;
enum CpuTopologyLevel t;
for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;
cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {
t = machine_get_cache_topo_level(ms, cache_level);
if (t == topo_level) {
/* Assume L1 is split into L1d and L1i caches. */
if (cache_level == CACHE_LEVEL_AND_TYPE_L1D ||
cache_level == CACHE_LEVEL_AND_TYPE_L1I) {
*lowest_cache_level = 1; /* L1 */
} else {
/* Assume the other caches are unified. */
*lowest_cache_level = cache_level;
}
return true;
}
}
return false;
}
/*
* Check if there are caches defined at a particular level. It supports only
* L1, L2 and L3 caches, but this can be extended to more levels as needed.
*
* Return True on success, False otherwise.
*/
bool machine_defines_cache_at_topo_level(const MachineState *ms,
CpuTopologyLevel topology)
{
enum CacheLevelAndType cache_level;
for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;
cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {
if (machine_get_cache_topo_level(ms, cache_level) == topology) {
return true;
}
}
return false;
}

5
include/hw/core/boards.h
View File

@@ -60,6 +60,11 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
CpuTopologyLevel level);
bool machine_check_smp_cache(const MachineState *ms, Error **errp);
void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
bool machine_defines_cache_at_topo_level(const MachineState *ms,
CpuTopologyLevel topology);
bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
int *lowest_cache_level,
CpuTopologyLevel topo_level);
/**
* machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices