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target/arm: Allow 'aarch64=off' to be set for TCG CPUs

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Allow the 'aarch64=off' property, which is currently KVM-only, to
be set for TCG CPUs also.

Note that we don't permit it on the qemu-aarch64 user-mode binary:
this makes no sense as that executable can only handle AArch64
syscalls (and it would also assert at startup since it doesn't
compile in the A32-specific GDB xml files like arm-neon.xml).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260416165353.589569-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
2026-04-16 17:53:52 +01:00
parent 95146de5d2
commit 970ea8478c
4 changed files with 45 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
docs/system/arm/cpu-features.rst
View File

@@ -23,10 +23,12 @@ not implement ARMv8-A, will not have the ``aarch64`` CPU property.
QEMU's support may be limited for some CPU features, only partially
supporting the feature or only supporting the feature under certain
configurations. For example, the ``aarch64`` CPU feature, which, when
disabled, enables the optional AArch32 CPU feature, is only supported
when using the KVM accelerator and when running on a host CPU type that
supports the feature. While ``aarch64`` currently only works with KVM,
it could work with TCG. CPU features that are specific to KVM are
disabled, enables the optional AArch32 CPU feature, can only be set to
``off`` on the TCG and KVM accelerators, and it cannot be set to
``off`` under KVM unless running on a host CPU type that supports
running guests in AArch32.
CPU features that are inherently specific to KVM are
prefixed with "kvm-" and are described in "KVM VCPU Features".
CPU Feature Probing

5
target/arm/cpu-features.h
View File

@@ -1071,6 +1071,11 @@ static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;
}
static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2;
}
static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;

36
target/arm/cpu.c
View File

@@ -1244,10 +1244,38 @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
* uniform execution state like do_interrupt.
*/
if (value == false) {
if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
error_setg(errp, "'aarch64' feature cannot be disabled "
"unless KVM is enabled and 32-bit EL1 "
"is supported");
if (kvm_enabled()) {
if (!kvm_arm_aarch32_supported()) {
error_setg(errp, "'aarch64' feature cannot be disabled for KVM "
"because this host does not support 32-bit EL1");
return;
}
} else if (tcg_enabled()) {
#ifdef CONFIG_USER_ONLY
error_setg(errp, "'aarch64' feature cannot be disabled for "
"usermode emulator qemu-aarch64; use qemu-arm instead");
return;
#else
bool aa32_at_highest_el;
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el3, cpu);
} else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el2, cpu);
} else {
aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el1, cpu);
}
if (!aa32_at_highest_el) {
error_setg(errp, "'aarch64' feature cannot be disabled for "
"this TCG CPU because it does not support 32-bit "
"execution at its highest implemented exception "
"level");
return;
}
#endif
} else {
error_setg(errp, "'aarch64' feature cannot be disabled for "
"this accelerator");
return;
}
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);

8
tests/qtest/arm-cpu-features.c
View File

@@ -493,12 +493,8 @@ static void test_query_cpu_model_expansion(const void *data)
sve_tests_default(qts, "max");
pauth_tests_default(qts, "max");
/* Test that features that depend on KVM generate errors without. */
assert_error(qts, "max",
"'aarch64' feature cannot be disabled "
"unless KVM is enabled and 32-bit EL1 "
"is supported",
"{ 'aarch64': false }");
/* TCG allows us to turn off AArch64 on the 'max' CPU type */
assert_set_feature(qts, "max", "aarch64", false);
}
qtest_quit(qts);