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hw/riscv: Register generic riscv[32|64] QOM interfaces

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Defines generic 32- and 64-bit riscv machine interfaces for machines to
implement.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Anton Johansson
2025-04-30 13:34:40 +02:00
committed by Philippe Mathieu-Daudé
parent 3f89b5de5b
commit a045f6a8e8
2 changed files with 29 additions and 0 deletions
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20
include/hw/riscv/machines-qom.h Normal file
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@@ -0,0 +1,20 @@
/*
* QOM type definitions for riscv32 / riscv64 machines
*
* Copyright (c) rev.ng Labs Srl.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_RISCV_MACHINES_QOM_H
#define HW_RISCV_MACHINES_QOM_H
#include "hw/core/boards.h"
#define TYPE_TARGET_RISCV32_MACHINE \
"target-info-riscv32-machine"
#define TYPE_TARGET_RISCV64_MACHINE \
"target-info-riscv64-machine"
#endif

9
target-info-qom.c
View File

@@ -13,6 +13,7 @@
#include "qemu/target-info-init.h" #include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h" #include "qemu/target-info-qom.h"
#include "hw/arm/machines-qom.h" #include "hw/arm/machines-qom.h"
#include "hw/riscv/machines-qom.h"
static const TypeInfo target_info_types[] = { static const TypeInfo target_info_types[] = {
{ {
@@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] = {
.name = TYPE_TARGET_AARCH64_MACHINE, .name = TYPE_TARGET_AARCH64_MACHINE,
.parent = TYPE_INTERFACE, .parent = TYPE_INTERFACE,
}, },
{
.name = TYPE_TARGET_RISCV32_MACHINE,
.parent = TYPE_INTERFACE,
},
{
.name = TYPE_TARGET_RISCV64_MACHINE,
.parent = TYPE_INTERFACE,
},
}; };
DEFINE_TYPES(target_info_types) DEFINE_TYPES(target_info_types)