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a045f6a8e8
Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21 lines
404 B
C
21 lines
404 B
C
/*
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* QOM type definitions for riscv32 / riscv64 machines
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*
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* Copyright (c) rev.ng Labs Srl.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_RISCV_MACHINES_QOM_H
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#define HW_RISCV_MACHINES_QOM_H
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#include "hw/core/boards.h"
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#define TYPE_TARGET_RISCV32_MACHINE \
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"target-info-riscv32-machine"
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#define TYPE_TARGET_RISCV64_MACHINE \
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"target-info-riscv64-machine"
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#endif
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