qemu/include/hw/riscv at a045f6a8e819dcc0e80d13fbd1cedf60c85cef79 - qemu

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Files

Anton Johansson a045f6a8e8 hw/riscv: Register generic riscv[32|64] QOM interfaces

Defines generic 32- and 64-bit riscv machine interfaces for machines to
implement.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

2026-05-27 08:03:27 +02:00

boot_opensbi.h

hw/riscv: Widen OpenSBI dynamic info struct

2025-10-28 08:19:18 +01:00

boot.h

hw/riscv: Treat kernel_start_addr as vaddr

2025-12-30 20:38:40 +01:00

cps.h

hw/riscv: Fix integer overflow in cm_base calculation

2026-03-19 14:28:16 +10:00

iommu.h

all: Clean up includes