hw/riscv: Register generic riscv[32|64] QOM interfaces

Defines generic 32- and 64-bit riscv machine interfaces for machines to
implement.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

include/hw/riscv/machines-qom.h

@@ -0,0 +1,20 @@
+/*
+ * QOM type definitions for riscv32 / riscv64 machines
+ *
+ *  Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_RISCV_MACHINES_QOM_H
+#define HW_RISCV_MACHINES_QOM_H
+
+#include "hw/core/boards.h"
+
+#define TYPE_TARGET_RISCV32_MACHINE \
+        "target-info-riscv32-machine"
+
+#define TYPE_TARGET_RISCV64_MACHINE \
+        "target-info-riscv64-machine"
+
+#endif

target-info-qom.c

@@ -13,6 +13,7 @@
 #include "qemu/target-info-init.h"
 #include "qemu/target-info-qom.h"
 #include "hw/arm/machines-qom.h"
+#include "hw/riscv/machines-qom.h"
 
 static const TypeInfo target_info_types[] = {
     {
@@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] = {
         .name           = TYPE_TARGET_AARCH64_MACHINE,
         .parent         = TYPE_INTERFACE,
     },
+    {
+        .name           = TYPE_TARGET_RISCV32_MACHINE,
+        .parent         = TYPE_INTERFACE,
+    },
+    {
+        .name           = TYPE_TARGET_RISCV64_MACHINE,
+        .parent         = TYPE_INTERFACE,
+    },
 };
 
 DEFINE_TYPES(target_info_types)