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qemu-options.hx: Document arm-smmuv3 device's accel properties

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Document arm-smmuv3 properties for setting HW-acceleration,
Range Invalidation, and Address Translation Services support, as
well as setting Output Address size and Substream ID size.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>
Tested-by: Shameer Kolothum <skolothumtho@nvidia.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
Message-id: 20260323182454.1416110-9-nathanc@nvidia.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Nathan Chen
2026-03-24 14:02:30 +00:00
committed by Peter Maydell
parent c2ff1305cc
commit af35bc0c14
1 changed files with 31 additions and 1 deletions
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qemu-options.hx
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@@ -1279,13 +1279,43 @@ SRST
``aw-bits=val`` (val between 32 and 64, default depends on machine)
This decides the address width of the IOVA address space.
``-device arm-smmuv3,primary-bus=id``
``-device arm-smmuv3,primary-bus=id[,option=...]``
This is only supported by ``-machine virt`` (ARM).
``primary-bus=id``
Accepts either the default root complex (pcie.0) or a
pxb-pcie based root complex.
``accel=on|off`` (default: off)
Enables guest to leverage host SMMUv3 features for acceleration.
Enabling accel configures the host SMMUv3 in nested mode to support
vfio-pci passthrough.
The following options are available when accel=on.
Note: 'auto' mode is not currently supported.
``ril=on|off`` (default: on)
Support for Range Invalidation, which allows the SMMUv3 driver to
invalidate TLB entries for a range of IOVAs at once instead of issuing
separate commands to invalidate each page. Must match with host SMMUv3
Range Invalidation support.
``ats=on|off`` (default: off)
Support for Address Translation Services, which enables PCIe devices to
cache address translations in their local TLB and reduce latency. Host
SMMUv3 must support ATS in order to enable this feature for the vIOMMU.
``oas=val`` (supported values are 44 and 48. default: 44)
Sets the Output Address Size in bits. The value set here must be less
than or equal to the host SMMUv3's supported OAS, so that the
intermediate physical addresses (IPA) consumed by host SMMU for stage-2
translation do not exceed the host's max supported IPA size.
``ssidsize=val`` (val between 0 and 20. default: 0)
Sets the Substream ID size in bits. When set to a non-zero value,
PASID capability is advertised to the vIOMMU and accelerated use cases
such as Shared Virtual Addressing (SVA) are supported.
``-device amd-iommu[,option=...]``
Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).
Only available with ``-machine q35``, it supports the following options: