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target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2026-06-09 12:21:07 -07:00
committed by Peter Maydell
parent 97f97d15c7
commit c44e030bdb
5 changed files with 33 additions and 0 deletions
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5
target/arm/cpu-features.h
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@@ -1650,6 +1650,11 @@ static inline bool isar_feature_aa64_f8mm8(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM8);
}
static inline bool isar_feature_aa64_f8mm4(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM4);
}
/*
* Combinations of feature tests, for ease of use with TRANS_FEAT.
*/

1
target/arm/tcg/a64.decode
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@@ -1228,6 +1228,7 @@ FDOT_sb_v 0.00 1110 000 ..... 11111 1 ..... ..... @qrrr_s
FDOT_hb_v 0.00 1110 010 ..... 11111 1 ..... ..... @qrrr_h
FMMLA_sb 0110 1110 100 ..... 11101 1 ..... ..... @rrr_q1e0
FMMLA_hb 0110 1110 000 ..... 11101 1 ..... ..... @rrr_q1e0
### Advanced SIMD scalar x indexed element

25
target/arm/tcg/fp8_helper.c
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@@ -832,3 +832,28 @@ void HELPER(gvec_fmmla_sb)(void *vd, void *vn, void *vm,
clear_tail(vd, oprsz, simd_maxsz(desc));
}
void HELPER(gvec_fmmla_hb)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
FP8MulContext ctx = fp8_mul_start(env, 0xf);
size_t oprsz = simd_oprsz(desc);
size_t nseg = oprsz / 8;
uint32_t *n = vn;
uint32_t *m = vm;
float16 *d = vd;
for (size_t seg = 0; seg < nseg; seg++, d += 4, n += 2, m += 2) {
float16 d0 = f8dotadd_h(n[H4(0)], m[H4(0)], 4, d[H2(0)], &ctx);
float16 d1 = f8dotadd_h(n[H4(0)], m[H4(1)], 4, d[H2(1)], &ctx);
float16 d2 = f8dotadd_h(n[H4(1)], m[H4(0)], 4, d[H2(2)], &ctx);
float16 d3 = f8dotadd_h(n[H4(1)], m[H4(1)], 4, d[H2(3)], &ctx);
d[H2(0)] = d0;
d[H2(1)] = d1;
d[H2(2)] = d2;
d[H2(3)] = d3;
}
clear_tail(vd, oprsz, simd_maxsz(desc));
}

1
target/arm/tcg/helper-fp8-defs.h
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@@ -37,3 +37,4 @@ DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)

1
target/arm/tcg/translate-a64.c
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@@ -7516,6 +7516,7 @@ static bool do_f8dot(DisasContext *s, arg_qrrr_e *a,
TRANS_FEAT(FDOT_sb_v, aa64_f8dp4, do_f8dot, a, gen_helper_gvec_fdot_sb)
TRANS_FEAT(FDOT_hb_v, aa64_f8dp2, do_f8dot, a, gen_helper_gvec_fdot_hb)
TRANS_FEAT(FMMLA_sb, aa64_f8mm8, do_f8dot, a, gen_helper_gvec_fmmla_sb)
TRANS_FEAT(FMMLA_hb, aa64_f8mm4, do_f8dot, a, gen_helper_gvec_fmmla_hb)
static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,
gen_helper_gvec_3_ptr *fn)