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target/riscv: Apply UXL WARL handling to vsstatus

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write_mstatus() already handles the reserved UXL value by writing a
legal value instead.

Apply the same handling when writing vsstatus so that reserved UXL
values follow the same WARL behavior.

Factor the common logic into a local helper riscv_write_uxl() and use
it for both mstatus and vsstatus.

Suggested-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Fixes: f310df58bd ("target/riscv: Enable uxl field write")
Signed-off-by: SeungJu Cheon <suunj1331@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260625081521.595683-1-suunj1331@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
SeungJu Cheon
2026-06-25 17:15:21 +09:00
committed by Alistair Francis
parent 13c2fc34f1
commit dcd0285177
1 changed files with 17 additions and 10 deletions
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27
target/riscv/csr.c
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@@ -2021,6 +2021,20 @@ static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
return val;
}
static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
uint64_t field)
{
RISCVMXL xl = riscv_cpu_mxl(env);
uint64_t uxl = get_field(val, field);
if (uxl == MXL_RV128) {
uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
val = set_field(val, field, uxl);
}
return val;
}
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
@@ -2067,17 +2081,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
if (xl != MXL_RV32 || env->debugger) {
if ((val & MSTATUS64_UXL) != 0) {
uint64_t uxl = val & MSTATUS64_UXL >> 32;
mask |= MSTATUS64_UXL;
/*
* uxl = 3 is reserved so write the current xl instead.
* In case xl = MXL_RV128 (3) write MXL_RV64.
*/
if (uxl == 3) {
uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
val = deposit64(val, 32, 2, uxl);
}
val = riscv_write_uxl(env, val, MSTATUS64_UXL);
}
}
@@ -5239,6 +5244,8 @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
uint64_t mask = (target_ulong)-1;
if ((val & VSSTATUS64_UXL) == 0) {
mask &= ~VSSTATUS64_UXL;
} else {
val = riscv_write_uxl(env, val, VSSTATUS64_UXL);
}
if ((env->henvcfg & HENVCFG_DTE)) {
if ((val & SSTATUS_SDT) != 0) {