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linux-user/riscv: honor zicntr=false for base counterCSRs

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In user-only builds, the base cycle and instret CSRs bypass the zicntr
feature gate because the check is inside the system-mode block. Move the
check before the conditional block so an explicitly disabled zicntr
extension makes the CSRs illegal in linux-user mode.

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4148

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
wangyang
2026-09-11 09:54:57 +08:00
committed by Helge Deller
parent e8dca265c9
commit ebfde6daff
1 changed files with 7 additions and 4 deletions
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11
target/riscv/tcg/csr.c
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@@ -111,6 +111,13 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno)
{
if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
(csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
if (!riscv_cpu_cfg(env)->ext_zicntr) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
#if !defined(CONFIG_USER_ONLY)
RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
@@ -127,10 +134,6 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
(csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
if (!riscv_cpu_cfg(env)->ext_zicntr) {
return RISCV_EXCP_ILLEGAL_INST;
}
goto skip_ext_pmu_check;
}