Clean up the codebase by removing the outdated DEBUG_IMX_EPIT
and DPRINTF macros, replacing them with modern QEMU trace events.
This also removes an empty and meaningless DPRINTF("\n") in the
imx_epit_realize function.
Signed-off-by: jack wang <163wangjack@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-id: 20260617161406.14705-1-163wangjack@gmail.com
[PMM: remove stray blank lines from bottom of trace-events file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Changes:
- [PATCH v3] docs/system: add general note about architecture and (Linisha <linisha232@gmail.com>)
Link: https://lore.kernel.org/qemu-devel/20260626181118.1136-1-linisha232@gmail.com
# -----BEGIN PGP SIGNATURE-----
#
# iQGzBAABCgAdFiEEN8FWlNi6l2Sxlz/btEQ30ZwoYt8FAmo+zu4ACgkQtEQ30Zwo
# Yt/NQwv+M30mFcGyX1sDBk3G/YTsrDaVsXmHIut4Iuz01jGkCkyR0Vqz/g3gmLTX
# Rouhgov7yzhmiU9XDzK+4SKPkiNCPCAH0Z3EBhYxy/kI9yXCBO9Qp89SbBVpG4BS
# efj6n+gUsojSHfvswp3OBomCxT9MziytCQ2ouNflBEiigPrBHhSTuDU8cgsmcx2E
# disJhObtYuC6UnHQc1wEZDboVsRWPO81RKATmv4mnQIJ1k6SZHPp8pxf09ku+gi2
# IrZZq5tOY1/N974NCFSyLzIUuY98r5hVCvxnMqyXavGVvTfdTIGowwmG5E4w/68J
# zk4ZoJpHUW2fXIfQFHTln7SKtdFsKsUmgTV/PxPG9w6EjSxDMoBHeYhbRKqIbbDW
# +AQymgH7Y2jAuZXpRiynbm/b5gzkYJT8tX8ffmN+0F7LWbiE4XWQD7y35AkgMCct
# TV8oY1HbPjEK5o6hr+TuYq0p5yF0feqAW8gUHUvDhNsIlifkbAyaFYuYCE+7l7RP
# z7Y6K43u
# =xXlR
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 26 Jun 2026 15:11:42 EDT
# gpg: using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197 3FDB B444 37D1 9C28 62DF
* tag 'pbouvier/pr/docs-20260626' of https://gitlab.com/p-b-o/qemu:
docs/system: add general note about architecture and machine differences
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target/i386/mshv: CPU model support
* target/i386/mshv: first part of migration support
* target/i386/mshv: faster register access for MMIO exits
* target/i386/tdx: add support for AMX alias bits in CPUID and AVX10
* Deprecate memory-encryption in favor of confidential-guest-support
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmo9sDwUHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroOHBwf8Dx4gkbzOFxmCNX3EaW+ROYwlyAC7
# ADo9LFloDHXforRYTm4mBXNUVNF1/KFA6Tf92rzBlUZgp9KuMy/KhWZ1GbNsE+9b
# k5/1RF9/IxRHy6GL69apdHEKY2OYzXl76or2HF3wMd6Mu77qD8Onthko81VaLWox
# 5ZOBz6NaSnykzs9RimkVLtD9HswtFile2NWTPSliUV874lEJioNi9RcdhnQvJCnX
# WqGWViC0THucIGCm+NVhSEmvRnAFbPgUBPvQuy7skLu+R7Ryy7GAWmE/gFlSrYy2
# 4c4zt4SB0tFYJlT9db5ZdaUSgCs52CFawQ9uTSEjNSmEEuQFzXGo6BeY4w==
# =4V0w
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 25 Jun 2026 18:48:28 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (45 commits)
i386/tdx: Add CPUID_24_0_EBX_AVX10_VL_MASK as supported
i386/tdx: Make AMX alias bits supported
i386/tdx: Use .has_gpa field to check if the gpa is valid
machine: Deprecate memory-encryption
qemu-options: Add description of tdx-guest object
qemu-options: Add confidential-guest-support to machine options
qemu-options: Change memory-encryption to confidential-guest-support in the example
i386/sev: Remove the example that references memory-encryption
target/i386/mshv: use the register page to set registers
target/i386/mshv: use the register page to get registers
target/i386/mshv: hv_vp_register_page setup for the vcpu
include/hw/hyperv: add hv_vp_register_page struct definition
accel: remove unnecessary #ifdefs
target/i386/mshv: migrate CET/SS MSRs
target/i386/mshv: migrate MTRR MSRs
target/i386/mshv: migrate MSRs
target/i386/mshv: reconstruct hflags after load
target/i386/mshv: migrate XSAVE state
target/i386/mshv: migrate pending ints/excs
target/i386/mshv: move msr code to arch
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Changes:
- [PATCH v2 0/6] gitlab: expose more info about CI runner environment (=?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= <berrange@redhat.com>)
Link: https://lore.kernel.org/qemu-devel/20260624124657.2725376-1-berrange@redhat.com
# -----BEGIN PGP SIGNATURE-----
#
# iQGzBAABCgAdFiEEN8FWlNi6l2Sxlz/btEQ30ZwoYt8FAmo9qdAACgkQtEQ30Zwo
# Yt8wMwwAhjB7xy4Eu3gt+leYEq9Yfq44fFGAnBQlN1kvEJhYkxJIA0KSoTZHGSQ/
# Kn97Quhc4kUI4+VvW++pDLevRZ1L80bcKPIM1PtOv5+VKvzCpEjzso6xYodpXTB5
# XgoXgnfTrLagccVeQLObex7PYPVtiQRV0xGXpQSgDqzbxgczgeEqR6YuED7eZVaJ
# ya2JdrIGnpKRhaal+RoCfSnqkRVYvIqs1/CVW2a3VZAq9+kLsx22NceDmX4v22mU
# O/rV4NlfjQ/2FuJvr/Zdnq8RFMHZwFW/NitKWH8esdgXwShnScNq/w4cHS/8CiYC
# 0jq1PxMNuI6q9yjQrXxDMdzJaPjyFnjCFCEYCyZsl9Iokb1GnWVT8xDB07HHRXwL
# nH6YYepSEhlEhY2RFkR4lT9q4p2XoTXlASgxpn6MLu+4V+vuh2A47KNNuClmiLnL
# JQfeF4970RHuJOzxxlzcIpjxHJSxi4SjbGKIuQZ6Hu1eIVx4Tly2Xep4mxa5qCZN
# KIwoRaKZ
# =jvzH
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 25 Jun 2026 18:21:04 EDT
# gpg: using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197 3FDB B444 37D1 9C28 62DF
* tag 'pbouvier/pr/ci-20260625' of https://gitlab.com/p-b-o/qemu:
gitlab: greatly expand captured info about CI runner environment
gitlab: pull before_script logic into .base_meson_job_template
gitlab: pull ccache setup into .base_meson_ccache_job_template
gitlab: use .base_meson_job_template from crossbuild jobs
gitlab: move .meson_job_template into base.yaml
gitlab: remove unused .cross_test_artifacts template
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Conflicts:
- .gitlab-ci.d/buildtest-template.yml
Context conflict with commit 559d834371 ("gitlab: ensure "check-XXX'
jobs capture functional test logs") moving the artifacts section.
testing and gitlab updates:
- present a dev friendly cmd line in functional test logs
- tell pylint to skip c-modules
- widen the capture of functional tests logs in gitlab
- remove workaround for MacOS build targets
- update the gitlab bug template for security process
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmo6W8MACgkQ+9DbCVqe
# KkRwDwf+NiRSwHfbjVSPOWws8wVSZHcgzeArHPsXtYrebi+rX9+l+bdIeRNFTfDX
# +6FvA5lWMbIB+pNFAkPdtjvpzzmV+tjaer6lR//0riF4Ch3TufYHhDVIjuvJaI/d
# mvsVUAFCS6AMb9sdky2mGA8SHeO5dV7XqMquTOH/tfs/M3PuLFMj8qcVFzXlmC79
# pzbpahCSJsclFj8traFYiAR2ofGXUH2PkW5aEctD1LnyAbGEHdEO8vR3KKB7ysHA
# OySKG0IXTBmyH03rZ9WHskVlH/xVZjo+FPro0moduTVOLeCksNBnuxdmKJKvPVVy
# vSrF/TOjZbmgg9vVlGULFNKTu3VlAQ==
# =2LgM
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 23 Jun 2026 06:11:15 EDT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-11.1-testing-updates-230626-1' of https://gitlab.com/stsquad/qemu:
gitlab: update bug template for sec issues & tool assistance
gitlab: remove build target hacks
gitlab: ensure "check-XXX' jobs capture functional test logs
tests/functional: tell pylint not to check c-modules
python/qemu: dump a developer friendly version of cmdline to logs
python/qemu: split console from harness args
python/qemu: split arg between base and harness lists
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
AVX10 depends on CPUID_24_0_EBX_AVX10_VL_MASK as defined in
feature_dependencies[]. Currently CPUID_24_0_EBX_AVX10_VL_MASK is always
not supported for TDX, so AVX10 cannot be exposed to TD guest.
The TDX virtualization type of these bits is "XFAM & CPUID_Enabled &
Native": their value is determined by XFAM[5:7], the AVX10 CPUID bit,
and the native hardware value.
For simplicity, add CPUID_24_0_EBX_AVX10_VL_MASK to tdx_xfam_deps[]
under the AVX512/XFAM dependency, without separately checking the AVX10
bit. It's safe because any invalid combination supplied by the user will
be caught by tdx_check_features().
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Tested-by: Chenyi Qiang <chenyi.qiang@intel.com>
Link: https://lore.kernel.org/r/20260512082108.621596-4-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
When booting a TD guest on a platform that supports AMX alias bits, QEMU
emits the warning such as:
qemu-system-x86_64: warning: TDX forcibly sets the feature: CPUID[eax=1Eh,ecx=01h].EAX.amx-int8-alias [bit 0]
...
Bit[3:0] of CPUID(0x1e,1).EAX alias the AMX CPUID bits from leaf 7.
Their TDX virtualization type is "CPUID_Enabled & Native": the value is
determined by the leaf-7 AMX bit they are aliased to and the native
hardware value.
These bits must be added to the TDX supported bits list so that they can
be enabled without triggering the forced-set warning. For simplicity,
mark them as supported whenever the corresponding AMX XFAM bit is
supported, rather than checking each aliased leaf-7 bit individually.
This reduces code complexity. Any platform that supports the AMX XFAM bit
but not these alias bits will still be handled correctly, since the TDX
module provides the real value via tdx_check_features().
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Tested-by: Chenyi Qiang <chenyi.qiang@intel.com>
Link: https://lore.kernel.org/r/20260512082108.621596-3-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
When translating the QAPI type GuestPanicInformationTdx into its C
struct, the generated code provides a .has_gpa boolean field to indicate
whether the optional gpa field is present.
Replace the magic sentinel value -1ULL, previously used to signal "no
valid GPA", with the idiomatic .has_gpa field. This removes the
implicit sentinel coupling and makes the validity check self-documenting.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Link: https://lore.kernel.org/r/20260512082108.621596-2-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
"confidential-guest-support" is the recommended property to configure
machine with confidential computing technology instead of
"memory-encryption".
Add "confidential-guest-support" to machine options and call out
explicitly "memory-encryption" is the alias of it and not recommended.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20260512084458.622465-4-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
"confidential-guest-support" is the recommended property to configure
sev for the machine, and amd-memory-encryption.rst has already switched
to use "confidential-guest-support" in the example.
Instead of changing "memory-encryption" to "confidential-guest-support"
in the comment of struct SevGuestState, just drop the example for
simplicity.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20260512084458.622465-2-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Change the mshv_load_regs to use the register page when it is mmapped
and is valid.
Otherwise use the existing logic that uses ioctls to fetch registers.
When retrieving the special registers, there are some registers that are
not present in the register page: TR, LDTR, GDTR, IDTR, CR2, APIC_BASE.
For this ones we still need to use ioctls to correctly fetch.
Signed-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260428135053.251200-6-dblanzeanu@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In this change the we rewrite the existing MSR logic to make MSRs
migratable:
- we map them on existing QEMU fields in the CPU. A table and a macro
MSHV_ENV_FIELD is used to associate a HV register name to the their msr
index and their offset in the cpu state struct. The list is not
exhaustive and will be extended in follow-up commits.
- mshv_set/get_msrs() fns are called in the arch_load/store_vcpu_state()
fns. they use use generic registers ioctl's and map the input/output
via load/store_to/from_env() from/to the hv register content to the
cpu state representation.
- init_msrs() has been moved from mshv-vcpu to the msr source file
- we need to perform some filtering of MSR because before writing and
reading, because the hvcalls will fail if the partition doesn't
support a given MSRs.
- Some MSRs are partition-wide and so we will only write the to on the
BSP.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260417105618.3621-21-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
We implement fn's that roundtrip XSAVE state in migration. We are using
the xsave_helper routines to move individual components from CPUX86State
to an xsave_buf and then we have to compact the buffer to XSAVEC format,
which is what the hypervisor expects.
And the same applies in the other direction for restoring state from the
hypervisor.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Link: https://lore.kernel.org/r/20260417105618.3621-32-magnuskulke@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
To aid in debugging wierd CI failures we need greater information
about the CI runner environment. It is usually container based
and can have some unexpected characteristics that significantly
differ from a developer's local environment.
This captures the mount list, CPU model, memory information,
device node lists, kernel info, user identity and all environment
variables.
Since this information can get quite large it is not emitted
directly in the logs, rather it is exposed in job artifacts
under the "ci-runner-env" directory.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260624124657.2725376-7-berrange@redhat.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Container image builds have started failing because zlib.net no longer
hosts the 1.3.1 tarball. Move to the 1.3.2 release from February 17,
2026.
$ make docker-image-emsdk-wasm64-cross
changing dir to build for make "docker-image-emsdk-wasm64-cross"...
make[1]: Entering directory 'qemu/build'
BUILD emsdk-wasm64-cross
...
xz: (stdin): File format not recognized
tar: Child returned status 1
tar: Error is not recoverable: exiting now
Error: building at STEP "RUN curl -Ls https://zlib.net/zlib-$ZLIB_VERSION.tar.xz | tar xJC /zlib --strip-components=1": while running runtime: exit status 2
make[1]: *** [qemu/tests/docker/Makefile.include:43: docker-image-emsdk-wasm64-cross] Error 2
make[1]: Leaving directory 'qemu/build'
make: *** [GNUmakefile:6: build] Error 2
Cc: Kohei Tokunaga <ktokunaga.mail@gmail.com>
Cc: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-id: 20260625193320.260312-1-stefanha@redhat.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
