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Author SHA1 Message Date
Daniel P. Berrangé
8b5ca42730 monitor: replace 'common' with 'parent_obj' in MonitorHMP 
The field name 'parent_obj' is standard practice for QOM structs
so align the HMP monitor.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
Tested-by: Peter Krempa <pkrempa@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20260706135824.2623960-3-berrange@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
 2026-07-07 11:16:22 +02:00
Daniel P. Berrangé
9c3b2c9db5 qom: replace 'can_be_deleted' with 'prepare_delete' 
While most objects can perform all their cleanup in the finalizer
method, there can be interactions with other resources / subsystems
/ threads which require that some cleanup be performed on an user
creatable object before unparenting it and entering finalization.

The current 'can_be_deleted' method runs in the deletion path and
is intended to be used to block deletion. While it could be used
to perform cleanup tasks, its name suggests it should be free of
side-effects.

Generalize this by renaming it to 'prepare_delete', explicitly
allowing for cleanup to be provided. Existing users of 'can_be_deleted'
are re-written, which provides them with more detailed/tailored error
messages.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20260706135824.2623960-2-berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
 2026-07-07 11:16:22 +02:00
Stefan Hajnoczi
94826ec137 Merge tag 'accel-20260706' of https://github.com/philmd/qemu into staging 
Accelerators patches queue

- Various cleanups around debugging APIs
- Correctly check singlestep flag enabled in CPUState
- Fix possible memory corruption with MSHV (CID 1660876)

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# gpg: Signature made Mon 06 Jul 2026 15:43:56 CEST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'accel-20260706' of https://github.com/philmd/qemu: (32 commits)
  cpu: Only check SSTEP_ENABLE flag in cpu_single_stepping()
  cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags
  cpu: Introduce cpu_single_stepping() helper
  cpu: Better name cpu_single_step() trace event
  accel/tcg: Improve docstrings around TCGCPUOps::*watchpoint* handlers
  target/ppc: Ensure TCG is used in ppc_update_daw()
  target/arm: Inline check_watchpoints() in arm_debug_check_watchpoint()
  accel: Use GdbBreakpointType enum
  gdbstub: Introduce GdbBreakpointType enumerator
  gdbstub: Reduce @type variable scope
  gdbstub/user: Directly call gdb_breakpoint_remove_all() in user mode
  accel: Remove unnecessary 'inline' qualifier in remove_all_breakpoints
  cpu: Move BREAKPOINT definitions to 'exec/breakpoint.h'
  cpu: Move cpu_breakpoint_test out of line
  accel: Remove AccelOpsClass::supports_guest_debug
  accel: Hold @can_reverse information in AccelGdbConfig
  gdbstub: Make default replay_mode value explicit in stubs
  accel: Have each implementation return their AccelGdbConfig
  gdbstub: Move supported_sstep_flags in AccelGdbConfig structure
  gdbstub: Reduce gdb_supports_guest_debug() scope
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:38:14 +02:00
Stefan Hajnoczi
d0edff8ee1 Merge tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu into staging 
target-arm queue:
 * hw/net/fsl_etsec: validate FCB offsets in process_tx_fcb()
 * hw/arm/smmuv3-accel: Fix veventq read returning true on EAGAIN/EINTR
 * target/arm: Only evaluate SCR_EL3.PIEN if ARM_FEATURE_EL3 is present
 * hw/arm: use cortex-a9 mpcore base for CBAR on npcm7xx machines
 * docs/specs/fw_cfg: Document all architecture register layouts
 * hw/nvram/fw_cfg: Simplify functions so board models don't have
   the opportunity to create non-standard fw_cfg register layouts
 * hw/misc: use tracepoints rather than DPRINTF in imx ccm models
 * hw/arm: add support for shim loading
 * docs/system/arm: Document Zynq Buildroot boot
 * target/arm: Report correct syndrome to AArch32 EL2 for trapped
   Neon/VFP insns
 * target/arm: implement WFET to not be a NOP
 * target/arm: Emulate FEAT_SME_MOP4
 * target/arm: Emulate FEAT_FPRCVT
 * target/arm: Emulate FEAT_SSVE_FEXPA

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# gpg: Signature made Mon 06 Jul 2026 12:36:41 CEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu: (49 commits)
  target/arm: Define fields for NSACR
  target/arm: Report correct syndrome to AArch32 EL2 for trapped Neon/VFP insns
  target/arm: Separate syndrome functions for A32 and A64
  target/arm: Separate out Neon from VFP access checks
  target/arm: Enable FEAT_SME_MOP4 for -cpu max
  target/arm: Implement USMOP4[AS]
  target/arm: Implement UMOP4[AS] (4-way)
  target/arm: Implement UMOP4[AS] (2-way)
  target/arm: Implement SUMOP4[AS]
  target/arm: Implement SMOP4[AS] (4-way)
  target/arm: Implement SMOP4[AS] (2-way)
  target/arm: Implement FMOP4A (widening, 2-way, FP8 to FP16)
  target/arm: Implement FMOP4 (widening, 4-way fp8 to fp32)
  target/arm: Implement FMOP4 (widening, 2-way fp16 to fp32)
  target/arm: Implement BFMOP4 (widening)
  target/arm: Implement BFMOP4 (non-widening)
  target/arm: Implement FMOP4 (non-widening) for float64
  target/arm: Implement FMOP4 (non-widening) for float16
  target/arm: Implement FMOP4 (non-widening) for float32
  docs/system/arm: Document Zynq Buildroot boot
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:37:28 +02:00
Stefan Hajnoczi
48560f0d96 Merge tag 'pull-ppc-for-11.1-sf-20260706' of https://gitlab.com/harshpb/qemu into staging 
PPC PR for 11.1 Soft-freeze

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# gpg: Signature made Mon 06 Jul 2026 10:20:12 CEST
# gpg:                using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [full]
# gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [full]
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-11.1-sf-20260706' of https://gitlab.com/harshpb/qemu:
  MAINTAINERS: Add self as maintainer for PowerNV
  ppc/pnv: Remove Power8E and Power8NVL CPUs
  ppc/pnv: Remove Power8E and Power8NVL pnv chips
  ppc/pnv: Replace Power8E with Power11 for 'none' machine test
  tests/functional: Use default powernv machine instead of power10
  tests/qtest: Add Power11 chip & machine to qtests
  tests/qtest/pnv_spi: Test Power11 PNV_SPI
  tests/functional: Add remote interrupts test for PowerNV

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:36:52 +02:00
Stefan Hajnoczi
9040c6f5c6 Merge tag 'hppa-fixes-for-v11.1-pull-request' of https://github.com/hdeller/qemu-hppa into staging 
Updates for hppa architecture for qemu v11.1

A few patches to fix TLB for HP-UX 9, and a lasi irq fix,
as well as a new SeaBIOS-hppa v25 firmware.

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# gpg: Signature made Sun 05 Jul 2026 17:47:05 CEST
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg:                 aka "Helge Deller <deller@debian.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'hppa-fixes-for-v11.1-pull-request' of https://github.com/hdeller/qemu-hppa:
  target/hppa: Update SeaBIOS-hppa to version 25
  hw/misc/lasi: derive IRR from pending and unmasked requests
  target/hppa: Delay MMU update until TLB protection bits were set
  target/hppa: Work-around for Fast TLB insert instruction on HP-UX 9

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:36:12 +02:00
Stefan Hajnoczi
9a84bbf230 Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging 
pci, vhost, virtio, iommu: features, fixes, cleanups

A new sp-mem device
New tests for vtd
New seg-max-adjust flag for vhost-user-blk
Watchdog support for arm/virt

Fixes, cleanups all over the place.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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# gpg: Signature made Sun 05 Jul 2026 15:19:16 CEST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (44 commits)
  virtio-net: validate RSS indirections_len in post_load
  vhost-user-blk: add seg-max-adjust flag
  vhost-user-scmi: free vhost virtqueue array on cleanup
  hw/virtio-crypto: enforce max akcipher key length
  vhost-user: Guarantee that memory regions do not overlap
  tests: acpi: arm/virt: update expected GTDT blob
  tests: acpi: arm/virt: add GTDT watchdog table test case
  tests: acpi: arm/virt: whitelist GTDT table
  tests: acpi: arm/virt: update expected WDAT blob
  tests: acpi: arm/virt: add WDAT table test case
  tests: acpi: arm/virt: whitelist new WDAT table
  arm: virt: add support for WDAT based watchdog
  acpi: introduce WDAT table for GWDT
  arm: sbsa-gwdt: add 'wdat' option
  arm: virt: create sbsa-gwdt watchdog
  arm: sbsa_gwdt: rename device type to sbsa-gwdt
  arm: add tracing events to sbsa_gwdt
  arm: sbsa_gwdt: fixup default "clock-frequency"
  vdpa: fix use-after-free of vqs in vhost_vdpa_device_unrealize
  vhost-user-base: clean up vhost_dev on realize failure
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:33:19 +02:00
Philippe Mathieu-Daudé
c0df53752c cpu: Only check SSTEP_ENABLE flag in cpu_single_stepping() 
Only the SSTEP_ENABLE bitmask means single-step is enabled.

Fixes: 60897d369f ("Debugger single step without interrupts")
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-33-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
7e28b7c897 cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags 
CPUState::singlestep_enabled contains multiple flags since
commit 60897d369f ("Debugger single step without interrupts").
Use an unsigned type and rename the field to avoid mistakes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-32-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
0a8bc0f251 cpu: Introduce cpu_single_stepping() helper 
Access CPUState::@singlestep_enabled field with a helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-31-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
d682cd181c cpu: Better name cpu_single_step() trace event 
cpu_single_step() is not related to breakpoints. Rename the
trace event.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260705215729.62196-30-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
93e7ca71d7 accel/tcg: Improve docstrings around TCGCPUOps::*watchpoint* handlers 
Commit d5ee641cfc ("target/ppc: Implement watchpoint debug facility
for v2.07S") also implemented TCGCPUOps::debug_check_watchpoint for
PPC: make the comment generic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-29-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
cbdbbfaf76 target/ppc: Ensure TCG is used in ppc_update_daw() 
Per commit d5ee641cfc ("target/ppc: Implement watchpoint debug
facility for v2.07S"), only TCG is implemented:

    ISA v2.07S introduced the watchpoint facility based on the DAWR0
    and DAWRX0 SPRs. Implement this in TCG.
                     ^^^^^^^^^^^^^^^^^^^^^

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260705215729.62196-28-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
0b55b519c6 target/arm: Inline check_watchpoints() in arm_debug_check_watchpoint() 
check_watchpoints() is called once, by arm_debug_check_watchpoint(),
which doesn't do more than this call. Merge both. No logical change
intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-27-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
0c4f68b2e3 accel: Use GdbBreakpointType enum 
Include '_gdbstub_' in the AccelOpsClass handlers to emphasize
we are handling gdbstub-related requests.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-26-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
af97fe2eaf gdbstub: Introduce GdbBreakpointType enumerator 
Introduce the GdbBreakpointType enumerator to better follow
code related to GDB protocol handling.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-25-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
85b6e24fa2 gdbstub: Reduce @type variable scope 
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-24-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
9285f1a215 gdbstub/user: Directly call gdb_breakpoint_remove_all() in user mode 
No need to deref external methods with unused argument to
end up calling a method defined in the same unit file, call
it directly.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-23-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
9dfa834009 accel: Remove unnecessary 'inline' qualifier in remove_all_breakpoints 
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-22-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
fe90b5f15b cpu: Move BREAKPOINT definitions to 'exec/breakpoint.h' 
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-20-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Richard Henderson
032731dbaf cpu: Move cpu_breakpoint_test out of line 
Move the function to cpu-common.c, with the other
breakpoint functions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260705215729.62196-19-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
0533f08413 accel: Remove AccelOpsClass::supports_guest_debug 
Now accelerators hold the 'guest debug supported' information
in their state, accessible by the common code. No need to call
a per-accelerator handler, simply check for the SSTEP_ENABLE
in AccelGdbConfig::sstep_flags.

Remove all AccelOpsClass::supports_guest_debug implementations,
inline gdb_supports_guest_debug() and remove the now unnecessary
KVMState::have_guest_debug field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-18-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
2aaa8ee7de accel: Hold @can_reverse information in AccelGdbConfig 
Hold @can_reverse in AccelGdbConfig, set it when initializing
AccelState in AccelClass::init_machine handlers (only TCG sets
it). Remove gdb_can_reverse() as now unused.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20260705215729.62196-17-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
d1286e2933 gdbstub: Make default replay_mode value explicit in stubs 
Make explicit @replay_mode is stubbed as REPLAY_MODE_NONE.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-16-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
8c60f7f38e accel: Have each implementation return their AccelGdbConfig 
Hold the per-accelerator AccelGdbConfig in AccelState, set its
single @sstep_flags field in AccelClass::init_machine handlers.

Remove the AccelClass::gdbstub_supported_sstep_flags() getter
and inline the single accel_supported_gdbstub_sstep_flags() call
in gdb_init_gdbserver_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-15-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
e9c5654035 gdbstub: Move supported_sstep_flags in AccelGdbConfig structure 
supported_sstep_flags are per-accelerators. Move them
to a new AccelGdbConfig structure, still in GDBState.

Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-14-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
5ba4a7d02b gdbstub: Reduce gdb_supports_guest_debug() scope 
gdb_supports_guest_debug() is only required for system emulation,
reduce its scope by making it private; remove the user emulation
variant.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260705215729.62196-13-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
f2468e2f49 accel/kvm: Hold have_guest_debug in KVMState 
Prefer to store per-accelerator variables in the per-accelerator
state, rather than as static variables. This is a good practice
to allow concurrent accelerators in the future.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-12-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
e32e858cf8 accel/kvm: Simplify kvm_init() w.r.t. TARGET_KVM_HAVE_GUEST_DEBUG 
Simplify #ifdef'ry using TARGET_KVM_HAVE_GUEST_DEBUG in kvm_init().
No need to zero-initialize kvm_sstep_flags again.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-11-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
0f66a69172 accel/kvm: Always define AccelOpsClass::supports_guest_debug 
Whether TARGET_KVM_HAVE_GUEST_DEBUG is defined or not,
kvm_supports_guest_debug() still exists and can be called.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-10-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
67ae20cc4a accel/whpx: Implement missing AccelClass::gdbstub_supported_sstep_flags 
Correct gdbstub support requires some gdbstub_supported_sstep_flags.
Apparently missed in commit d7482ffe97 ("whpx: Added support for
breakpoints and stepping"), even with the recent 19b48084f7 ("whpx:
i386: re-enable guest debug support") fixes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-9-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
82d97eeda8 gdbstub: Only return E22 when reverse GDB is not supported 
No need to keep processing the arguments when we know
reverse debugging is not available.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20260705215729.62196-8-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
32822e3898 gdbstub: Add trace event for STEP packet handler 
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20260705215729.62196-7-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Magnus Kulke
ce0b7a15bc accel/mshv: Fix pointer to proc feature bitfield 
Processor features are stored in a union containing two "banks":

union hv_partition_processor_features {
    uint64_t as_uint[2];
    struct {
        uint64_t sse3_support:1;
        ...
    }
}

get_proc_features() to retrieve the 2nd bank was passing a pointer that
steps over the whole union (+16B) instead of picking the 2nd bank _in_
the union. This manifests in mismatching feature bits for the 2nd bank
and possibly other side-effects caused by writing beyond the union.

We need to step over the first bank (+8B) by using as_uint64[0/1] to
correct this behaviour.

Resolves: Coverity CID 1660876
Fixes: 2f6da91e8a ("accel/mshv: store partition proc features")
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Reviewed-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20260701130335.418156-1-magnuskulke@linux.microsoft.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
abdd572a43 accel/mshv: Replace @dirty field by generic CPUState::vcpu_dirty field 
No need for accel-specific @dirty field when we have
a generic one in CPUState. (Other accelerators already
did that in commits 6f13a0ada01..36ab216b81d).

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Tested-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-6-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
586a25c492 accel/hvf: Remove left-over comment 
Missed in commit 6bf331164c ("accel/hvf: Drop hvf_slot and
hvf_find_overlap_slot").

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-5-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Philippe Mathieu-Daudé
cadee08114 accel/tcg: Restrict tlb_protect/unprotect_code() to TCG 
Both tlb_protect() and tlb_unprotect_code() are only used
within accel/tcg/. Avoid exposing them to the whole code base,
declare them in a new "system-page-protection.h" local header
(maintaining the previous LGPL-2.1-or-later license).

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260705215729.62196-4-philmd@oss.qualcomm.com>
 2026-07-06 15:41:34 +02:00
Philippe Mathieu-Daudé
c1b47f48eb target/i386: Remove duplicate tlb_flush() call in cpu_post_load() 
Common vCPU cpu_common_post_load() handler calls tlb_flush() since
commit 9656f324d2 ("Move interrupt_request and user_mode_only to
common cpu state..."), no need to call it twice.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260705215729.62196-3-philmd@oss.qualcomm.com>
 2026-07-06 14:57:07 +02:00
Philippe Mathieu-Daudé
65339110b7 cpu: Constify CPUState::cc (cached CPUClass pointer) 
Various CPUState can share the same CPUClass parent,
and must not update its fields. Protect the CPUClass
by marking the CPUState pointer const.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Message-ID: <20260705215729.62196-2-philmd@oss.qualcomm.com>
 2026-07-06 14:57:00 +02:00
Peter Maydell
3455eac92d target/arm: Define fields for NSACR 
Currently we handle cp15.nsacr with raw bit numbers in the few places
we need to work with it.  We're about to add some more uses of this
field, so define its fields with the FIELD macro and use the macros
in the places that were previously using bit numbers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702184019.3431139-5-peter.maydell@linaro.org
 2026-07-06 11:32:01 +01:00
Peter Maydell
da8179efd6 target/arm: Report correct syndrome to AArch32 EL2 for trapped Neon/VFP insns 
When an AArch32 Neon or VFP insn is trapped to AArch64 EL2, bits
[19:0] of the syndrome in ESR_EL2 are RES0.  However, when it is
trapped to AArch32 EL2, the HSR syndrome information defines some
extra fields:
 [5] : TA
 [3:0] : coproc

where the TA bit is 1 for a trapped Neon insn and 0 for a trapped
VFP insn, and the coproc field is 0b1010 when TA is 0, and 0 when
TA is 1.

We attempted to address this in commit fa33eead ("target/arm: Add
coproc parameter to syn_fp_access_trap"), but got it wrong: we
thought the RES0 condition was "is v8A" rather than "is EL2 AArch32",
and we made all insns be TA=0 coproc = 0b1010 rather than only the
VFP ones.  Correct the condition we use to decide the coproc and TA
fields.  We set these fields unconditionally; later on in
arm_cpu_do_interrupt_aarch64() we will squash them to zero if we are
taking the exception to AArch64.

NB: there is some disagreement between different revisions of the
Arm ARM about the exact handling of 'coproc':
 * the v8A Arm ARM text says coproc is 0b1010 when TA is 1
 * the v8A Arm ARM pseudocode in AArch32_CheckFPAdvSIMDTrap()
   sets coproc to 0b1010 when TA is 0
 * the v7A Arm ARM text says coproc is 0b1010 when TA is 0
 * the v7A Arm ARM pseudocode sets coproc to 0b1010 when TA is 0

The v7A Arm ARM pseudocode also disagrees with the v7A text, v8A text
and v8A pseudocode in only setting TA to 1 for traps caused by
HCPTR.TASE; the others set Ta for all trapped AdvSIMD insns
(i.e. including traps caused by HCPTR.TCP10).

We assume that the v8A pseudocode is incorrect about coproc (as it is
the odd one out) and that the v7A pseudocode is incorrect about when
TA is set (again, as it is the odd one out).

Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/1153
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702184019.3431139-4-peter.maydell@linaro.org
 2026-07-06 11:32:01 +01:00
Peter Maydell
59970c372c target/arm: Separate syndrome functions for A32 and A64 
Currently we have one syn_fp_access_trap() which we use for fp
traps from A64 and from VFP and Neon A32. This means that A64
has to specify arguments that are always fixed for it (coproc
and is_16bit) and A32 can't specify arguments it needs to (TA).

Split it up into syn_a64_fp_access_trap() and
syn_a32_fp_access_trap(). This is a refactor with no
behavioural change.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702184019.3431139-3-peter.maydell@linaro.org
 2026-07-06 11:32:01 +01:00
Peter Maydell
e8ffed006b target/arm: Separate out Neon from VFP access checks 
Currently we use vfp_access_check() for AArch32 VFP and Neon
instructions.  This is not quite right:
 * there are optional CPACR.ASEDIS and HCPTR.TASE controls that allow
   trapping of just the Neon and not VFP instructions
 * Neon instructions are supposed to report a slightly different
   syndrome in HCR when they trap to AArch32 EL2

As a preliminary refactor so we have somewhere we can make this
distinction, separate out Neon access checks into a separate
neon_access_check(), which initially just calls vfp_access_check().

The set of insns this needs to cover are those described in section
E1.3.9 of the DDI0487M.b Arm ARM.  For us this corresponds to
everything in neon-dp.decode and neon-ls.decode and thus in
translate-neon.c, plus three insns that we handle in translate-vfp.c:
 - VDUP (general-purpose register)
 - VMOV (general-purpose register to scalar) byte and halfword
 - VMOV (scalar to general-purpose register) byte and halfword
(which are the ones in that file with ARM_FEATURE_NEON checks).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702184019.3431139-2-peter.maydell@linaro.org
 2026-07-06 11:32:01 +01:00
Richard Henderson
82d7e57204 target/arm: Enable FEAT_SME_MOP4 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
48d9d26fbc target/arm: Implement USMOP4[AS] 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
bdd81a778a target/arm: Implement UMOP4[AS] (4-way) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
6a720251cb target/arm: Implement UMOP4[AS] (2-way) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
f1f8762cc4 target/arm: Implement SUMOP4[AS] 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
5d84977214 target/arm: Implement SMOP4[AS] (4-way) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
6162c1baa9 target/arm: Implement SMOP4[AS] (2-way) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00