Commit Graph

127858 Commits

Author SHA1 Message Date
Philippe Mathieu-Daudé
e0930f667a gdbstub: Emit base_register index in GDBFeature entries
Record the base register index in the generated C file.

Check at runtime that either @g_pos argument of
gdb_register_coprocessor() is zero, or it the base register
index.

This change pass 'make check-tcg' test suite, which runs the
tests/tcg/multiarch/gdbstub/registers.py test, itself calling
gdb_register_coprocessor() for each target tested.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-12-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
aa6a508795 gdbstub: Remove @g_pos argument in gdb_register_coprocessor()
gdb_register_coprocessor()'s @g_pos argument is always '0',
meaning it is inferred from cpu->gdb_num_regs. Use instead
feature->base_reg.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-11-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
9aad3f83a5 gdbstub: Make base register explicit in m68k GDB XML files
Both gdb-xml/cf-fp.xml and gdb-xml/m68k-fp.xml aren't imported
from GDB repository. Presumably they are hand-written, and lack
the @regnum XML tag.

This might explain why gdb_register_coprocessor() have a @g_pos
argument, only used for these 2 m68k files.

Fixes: 56aebc8916 ("Add GDB XML register description support")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-10-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
400b3633ff gdbstub: Have scripts/feature_to_c.py generate more verbose output
Make the structure field names explicit, so it is easier
to figure what is what when reviewing multiple entries.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-9-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
1e06ef47df gdbstub: Add trace events for around XML parsing / generation
Add trace events to help follow how the various files in
gdb-xml/ are parsed or generated at runtime.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-8-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
3b6cf87d42 gdbstub: Simplify gdb_init_cpu() logic
Ensure we either set gdb_num_core_regs or have a XML file.
We shouldn't modify CPUClass content, so mark it const.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-7-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
29e30df3f3 meson: Restrict gdbstub to user/system builds
Limited builds (tools, documentation) don't need to generate /
build gdbstub files. Only process the gdbstub/ folder when
user / system emulation / acceleration is built.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-6-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
541870763f target/i386/gdbstub: Remove stale comment
Since commit ecd6f6a882 ("gdbstub: Infer number of core
registers from XML") gdb_num_core_regs is inferred for
the x86 targets. Remove a stale comment.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-5-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Alex Bennée
5459318a25 tests/docker: add gdb-multiarch to all-test-cross
This allows the gdb integration tests to be run as well.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260306161728.2657486-2-alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-4-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
c0ca86f510 tests/tcg: Disable prot-none test on GitLab
When adding gdb-multiarch on our container images, we
see the prot-none tests to pass on GitHub but fail on
GitLab. Disable and track:
https://gitlab.com/qemu-project/qemu/-/issues/3329

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-3-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Philippe Mathieu-Daudé
c399ad4791 tests/tcg: Temporary disable multiarch tests for PPC targets
gdbstub is currently broken for the PPC targets [*]. We
didn't notice because our tests require gdb-multiarch which
isn't installed on our containers. Next patch will fix that,
but we need to temporary disable the PPC target test to keep
our CI green.

[*] https://lore.kernel.org/qemu-devel/e44df309-d40d-46f0-88a8-7ac55f9a3634@fhofhammer.de/

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <c957fe25-a0a2-405f-be83-d411261c21e6@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20260310232045.58440-2-philmd@linaro.org
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2026-03-10 17:12:18 -07:00
Peter Maydell
ae56950eac Merge tag 'firmware-20260310-pull-request' of https://gitlab.com/kraxel/qemu into staging
- firmware.json spec update for svsm.
- igvm bugfixes.

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# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* tag 'firmware-20260310-pull-request' of https://gitlab.com/kraxel/qemu:
  i386/sev/igvm: do not reset guest policy if IGVM does not set it
  igvm: fix build when igvm is not installed in a well known path
  docs/interop: Add AMD SEV-SNP SVSM interface to firmware.json

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 13:32:30 +00:00
Peter Maydell
9745100afc Merge tag 'pull-loongarch-20260310' of https://github.com/gaosong715/qemu into staging
loongarch bug fix

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* tag 'pull-loongarch-20260310' of https://github.com/gaosong715/qemu:
  target/loongarch: Avoid recursive PNX exception on CSR_BADI fetch
  target/loongarch: Preserve PTE permission bits in LDPTE

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 13:32:16 +00:00
Peter Maydell
89851dbcce Merge tag 'accel-tcg-20260310' of https://github.com/philmd/qemu into staging
Accelerators and TCG patches queue

- Improve TCG extract and deposit
- Build accelerator stub files once

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# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'accel-tcg-20260310' of https://github.com/philmd/qemu:
  accel/qtest: Build once as common object
  accel/xen: Build without target-specific knowledge
  accel/hvf: Build without target-specific knowledge
  accel/mshv: Build without target-specific knowledge
  accel/mshv: Forward-declare mshv_root_hvcall structure
  accel/stubs: Build stubs once
  accel/kvm: Make kvm_irqchip*notifier() declaration non target-specific
  accel/kvm: Include missing 'exec/cpu-common.h' header
  target/hppa: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64()
  tcg/optimize: possibly expand deposit into zero with shifts
  tcg: target-dependent lowering of extract to shr/and
  tcg: Add tcg_op_imm_match
  tcg: Expand missing rotri with extract2
  tcg/optimize: Lower unsupported extract2 during optimize
  tcg/optimize: Lower unsupported deposit during optimize
  tcg: Drop extract+shl expansions in tcg_gen_deposit_z_*

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 13:32:04 +00:00
Ani Sinha
470ccb470b i386/sev/igvm: do not reset guest policy if IGVM does not set it
The guest policy is set either through command-line or through IGVM. If none of
the above applies, default guest policy applies. However, if IGVM does not set
the guest policy, currently the policy gets set to 0 regardless of whether it
was previously set to default value or command line. This change fixes this by
checking if IGVM indeed has set a policy value. If not, do not reset existing
value.

This avoids guest crashes such as the following during reset when the IGVM
has not explicitly set any guest policies:

qemu-system-x86_64: sev_snp_launch_start: SNP_LAUNCH_START ret=-22 fw_error=0 ''
qemu-system-x86_64: sev_common_kvm_init: failed to create encryption context
qemu-system-x86_64: unable to rebuild guest: Operation not permitted(-1)

Reported-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-ID: <20260310094450.35861-3-anisinha@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2026-03-10 14:20:41 +01:00
rail5
db2325f794 target/loongarch: Avoid recursive PNX exception on CSR_BADI fetch
loongarch_cpu_do_interrupt() updates CSR_BADI by fetching the faulting
instruction with cpu_ldl_code_mmu().

For a PNX exception (instruction fetch prohibited by NX), fetching the
instruction at env->pc will fault with PNX again. This can lead to an
infinite exception loop.

Treat PNX like other instruction-fetch exceptions (PIF/ADEF) and do not
update CSR_BADI for it.

Fixes: 410dfbf620 ("target/loongarch: Move TCG specified functions to tcg_cpu.c")
Cc: qemu-stable@nongnu.org
Signed-off-by: rail5 (Andrew S. Rightenburg) <andrew@rail5.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
2026-03-10 19:50:01 +08:00
rail5
2d877bc02a target/loongarch: Preserve PTE permission bits in LDPTE
The LDPTE helper loads a page table entry (or huge page entry) from guest
memory and currently applies the PALEN mask to the whole 64-bit value.

That mask is intended to constrain the physical address bits, but masking
the full entry also clears upper permission bits in the PTE, including NX
(bit 62). As a result, LoongArch TCG can incorrectly allow instruction
fetches from NX mappings when translation is driven through software
page-walk.

Fix this by masking only the PPN/address field with PALEN while preserving
permission bits, and by clearing any non-architectural (software) bits
using a hardware PTE mask. LDDIR is unchanged since it returns the base
address of the next page table level.

Reported at: https://gitlab.com/qemu-project/qemu/-/issues/3319

Fixes: 56599a705f ("target/loongarch: Introduce loongarch_palen_mask()")
Cc: qemu-stable@nongnu.org
Signed-off-by: rail5 (Andrew S. Rightenburg) <andrew@rail5.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
2026-03-10 19:49:54 +08:00
Peter Maydell
4680a6605e Merge tag 'pull-request-2026-03-10' of https://gitlab.com/thuth/qemu into staging
- Improve the s390-ccw bios to be able to boot from virtio-blk-pci devices
- Rework migration functional test to avoid a problem in the ppc64 test
- Disable functional memlock test for asan builds
- Some other minor tests improvements

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# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [undefined]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2026-03-10' of https://gitlab.com/thuth/qemu: (25 commits)
  pc-bios/s390-ccw.img: Update the s390 bios blog with the latest changes
  pc-bios/s390-ccw: Fix compiler warning when compiling with DEBUG enabled
  tests/qtest: Add s390x PCI boot test to cdrom-test.c
  hw: Add "loadparm" property to virtio block PCI devices booting on s390x
  s390x: Build IPLB for virtio-pci devices
  pc-bios/s390-ccw: Add support for virtio-blk-pci IPL
  pc-bios/s390-ccw: Introduce virtio-pci functions
  pc-bios/s390-ccw: Introduce PCI device
  s390x: Add definitions for PCI IPL type
  pc-bios/s390-ccw: Introduce CLP Architecture
  include/hw/s390x: Move CLP definitions for easier BIOS access
  pc-bios/s390-ccw: Split virtio-ccw and generic virtio
  pc-bios/s390-ccw: Store device type independent of sense data
  s390x: Remove duplicate definitions of IPL types
  pc-bios/s390-ccw: Always reset virtio device on failed boot attempt
  pc-bios/s390-ccw: Remove redundant vring schid attribute
  pc-bios/s390-ccw: Fix misattributed function prototypes
  tests/functional/ppc64/pseries: Remove custom migration routine
  tests/functional/migration: Use the migrate_vms helper
  tests/functional/migration: Add migrate_vms
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 11:39:08 +00:00
Peter Maydell
56fe2ca5b6 Merge tag 'staging-pull-request' of https://gitlab.com/peterx/qemu into staging
Memory pull for 11.0 softfreeze

- BALATON's memory cleanups on _nomigrate MRs and else
- Phil's small constify series and else
- Marc-André's initial cleanup patches around ram discard manager

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# gpg: Signature made Mon Mar  9 20:38:51 2026 GMT
# gpg:                using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706
# gpg:                issuer "peterx@redhat.com"
# gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal]
# gpg:                 aka "Peter Xu <peterx@redhat.com>" [marginal]
# gpg: WARNING: The key's User ID is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D  D1A9 3B5F CCCD F3AB D706

* tag 'staging-pull-request' of https://gitlab.com/peterx/qemu:
  system/memory: Have memory_region_type() correctly describe containers
  system/xen: Constify various MemoryRegion arguments
  system/memory: Constify various MemoryRegion arguments
  system/ramblock: Constify various RAMBlock arguments
  kvm: replace RamDicardManager by the RamBlockAttribute
  system/memory: minor doc fix
  virtio-mem: use warn_report_err_once()
  memory: drop RamDiscardListener::double_discard_supported
  system/rba: use DIV_ROUND_UP
  memory: Factor out common ram ptr initialization
  memory: Factor out common ram region initialization
  memory: Add internal memory_region_register_ram function
  memory: Shorten memory_region_init_ram_device_ptr and memory_region_init_rom_device
  memory: Remove memory_region_init_ram_nomigrate()
  hw/xtensa/xtfpga: Do not use memory_region_init_ram_nomigrate()
  sun4m,sun4u,tcx: Do not use memory_region_init_ram_nomigrate()
  memory: Remove memory_region_init_rom_nomigrate()
  hw/display/{cg3.tcx}: Do not use memory_region_init_rom_nomigrate()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 11:38:58 +00:00
Philippe Mathieu-Daudé
c574ff9245 accel/qtest: Build once as common object
No code within qtest.c uses target-specific knowledge:
build it once as target-agnostic common unit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260225053408.18426-1-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
beaf63280a accel/xen: Build without target-specific knowledge
Code in accel/ aims to be target-agnostic. Enforce that
by moving the Xen file units to system_ss[], which is
target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Anthony PERARD <anthony.perard@vates.tech>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-6-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
593063e4cb accel/hvf: Build without target-specific knowledge
Code in accel/ aims to be target-agnostic. Enforce that
by moving the HVF file units to system_ss[], which is
target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-5-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
35f797739b accel/mshv: Build without target-specific knowledge
Code in accel/ aims to be target-agnostic. Enforce that
by moving the MSHV file units to system_ss[], which is
target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-4-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
591357b68f accel/mshv: Forward-declare mshv_root_hvcall structure
Forward-declare the target-specific mshv_root_hvcall structure
in order to keep 'system/mshv_int.h' target-agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-3-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
e78cc345db accel/stubs: Build stubs once
Move stubs to the global stub_ss[] source set. These files
are now built once for all binaries, instead of one time
per system binary.

Inspired-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225044225.64059-1-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
23e79ed4bf accel/kvm: Make kvm_irqchip*notifier() declaration non target-specific
Commit 3607715a30 ("kvm: Introduce KVM irqchip change notifier")
restricted the kvm_irqchip*notifier() declarations to target-specific
files, guarding them under the NEED_CPU_H (later renamed as
COMPILING_PER_TARGET) #ifdef check.

This however prohibit building the kvm-stub.c file once:

  ../accel/stubs/kvm-stub.c:70:6: error: no previous prototype for function 'kvm_irqchip_add_change_notifier' [-Werror,-Wmissing-prototypes]
     70 | void kvm_irqchip_add_change_notifier(Notifier *n)
        |      ^
  ../accel/stubs/kvm-stub.c:74:6: error: no previous prototype for function 'kvm_irqchip_remove_change_notifier' [-Werror,-Wmissing-prototypes]
     74 | void kvm_irqchip_remove_change_notifier(Notifier *n)
        |      ^
  ../accel/stubs/kvm-stub.c:78:6: error: no previous prototype for function 'kvm_irqchip_change_notify' [-Werror,-Wmissing-prototypes]
     78 | void kvm_irqchip_change_notify(void)
        |      ^

Since nothing in these prototype declarations is target specific,
move them around to be generically available, allowing to build
kvm-stub.c once for all targets in the next commit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260309174941.67624-2-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
43f507555d accel/kvm: Include missing 'exec/cpu-common.h' header
kvm-accel-ops.c uses EXCP_DEBUG, itself defined in
"exec/cpu-common.h". Include it explicitly, otherwise
we get when modifying unrelated headers:

  ../accel/kvm/kvm-accel-ops.c: In function ‘kvm_vcpu_thread_fn’:
  ../accel/kvm/kvm-accel-ops.c:54:22: error: ‘EXCP_DEBUG’ undeclared (first use in this function)
     54 |             if (r == EXCP_DEBUG) {
        |                      ^~~~~~~~~~

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260225051303.91614-2-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Philippe Mathieu-Daudé
784d12cada target/hppa: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64()
The HPPA target is a 64-bit one, so tcg_global_mem_new()
expands to tcg_global_mem_new_i64(). Use the latter which
is more explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260205212914.10382-1-philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Richard Henderson
744eb39667 tcg/optimize: possibly expand deposit into zero with shifts
Use tcg_op_imm_match to choose between expanding with AND+SHL vs SHL+SHR.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260303010833.1115741-8-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Paolo Bonzini
bfe9264835 tcg: target-dependent lowering of extract to shr/and
Instead of assuming only small immediates are available for AND,
consult the backend in order to decide between SHL/SHR and SHR/AND.

Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[rth: Split from a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260303010833.1115741-7-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Paolo Bonzini
bb5b6bbb10 tcg: Add tcg_op_imm_match
Create a function to test whether the second operand of a
binary operation allows a given immediate.

Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[rth: Split out from a larger patch; keep the declaration internal.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260303010833.1115741-6-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Richard Henderson
6cced95c28 tcg: Expand missing rotri with extract2
Use extract2 to implement rotri.  To make this easier,
redefine rotli in terms of rotri, rather than the reverse.

Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260303010833.1115741-5-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Richard Henderson
e4cebfc664 tcg/optimize: Lower unsupported extract2 during optimize
The expansions that we chose in tcg-op.c may be less than optimal.
Delay lowering until optimize, so that we have propagated constants
and have computed known zero/one masks.

Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260303010833.1115741-4-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Richard Henderson
5f747705a4 tcg/optimize: Lower unsupported deposit during optimize
The expansions that we chose in tcg-op.c may be less than optimal.
Delay lowering until optimize, so that we have propagated constants
and have computed known zero/one masks.

Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260303010833.1115741-3-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Richard Henderson
c1d5ef32e7 tcg: Drop extract+shl expansions in tcg_gen_deposit_z_*
The extract+shl expansion is handled in tcg_gen_andi_*
by preferring supported extract.

The shl+extract expansion is simply removed for now; it was
only present for slightly smaller code generation on x86.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260303010833.1115741-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2026-03-10 11:36:21 +01:00
Peter Maydell
63ec1f7694 Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging
Python pullreq

Drop avocado, support Python3.14. Fixes optional check-python-tox GitLab
CI test.

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# gpg: Signature made Mon Mar  9 18:05:31 2026 GMT
# gpg:                using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* tag 'python-pull-request' of https://gitlab.com/jsnow/qemu:
  python: add formal python3.14 support and testing
  python: drop avocado
  python: replace avocado tests with pytest
  python: pin 'wheel' version in minreqs test

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 09:32:50 +00:00
Peter Maydell
be7f1c297c Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* hvf/x86: compilation fixes
* whpx: fixes
* xen-block: fix possible NULL pointer dereference
* coroutine-lock: fix thinko

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# gpg: Signature made Mon Mar  9 08:13:00 2026 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  whpx: i386: remove SIPI trapping
  whpx: arm64: enable enlightenments if asked for
  whpx: make Hyper-V enlightenments configurable
  whpx: i386: enable some more enlightenments
  target/i386: emulate: LA57 fix
  whpx: i386: do not enable nested virt when kernel-irqchip=off
  hvf: arm: unbreak the x86 build
  target/i386/hvf/hvf.c: fix compilation
  qemu-coroutine-lock: fix has_waiters()
  xen-block: remove NULL pointer dereference

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-03-10 09:32:17 +00:00
Luigi Leonardi
5c45204e34 igvm: fix build when igvm is not installed in a well known path
`stubs/igvm.c` includes `igvm-internal.h`, that in turn includes the igvm library.
This is required just for the QIgvm declaration and creates an
unnecessary dependency on the library.

Since igvm is not listed as a dependency of stubs, this results in build
failing when the library is not installed in a "well known" path of the
system.

Add a forward declaration for QIgvm and move the definition of
`qigvm_directive_madt` to `igvm.h` so that we can drop `igvm-internal.h` from
`stubs/igvm.c`.

Fixes: dea1f68a5c ("igvm: Fill MADT IGVM parameter field on x86_64")
Suggested-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Luigi Leonardi <leonardi@redhat.com>
Message-ID: <20260309-master-v2-1-7e02f07a1096@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2026-03-10 08:57:05 +01:00
Oliver Steffen
c221dd7746 docs/interop: Add AMD SEV-SNP SVSM interface to firmware.json
AMD SEV-SNP defines a guest to Secure VM Service Module (SVSM) firmware
[1] interface. Add a corresponding item to the FirmwareOSInterface
enum.

[1]
https://docs.amd.com/api/khub/documents/Al5Q~fSl~kWKkJ3zC0vk_g/content

Signed-off-by: Oliver Steffen <osteffen@redhat.com>
Message-ID: <20260123083204.999920-3-osteffen@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2026-03-10 08:44:49 +01:00
Thomas Huth
f2bd9693f2 pc-bios/s390-ccw.img: Update the s390 bios blog with the latest changes
- Make sure the reset virtio devices on failed boot attempts
- Add support for booting via virtio-blk-pci

Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Thomas Huth
14c29f2906 pc-bios/s390-ccw: Fix compiler warning when compiling with DEBUG enabled
When compiling with DEBUG=1, there is currently a compiler warning:

 pc-bios/s390-ccw: Compiling main.o
 In file included from /home/thuth/devel/qemu/pc-bios/s390-ccw/main.c:14:
 In file included from /home/thuth/devel/qemu/pc-bios/s390-ccw/helper.h:16:
 /home/thuth/devel/qemu/pc-bios/s390-ccw/s390-ccw.h:122:31: warning: format specifies type
       'unsigned int' but the argument has type 'u64' (aka 'unsigned long long') [-Wformat]
   122 |     printf("%s 0x%X\n", desc, addr);
       |                  ~~           ^~~~
       |                  %llX
 1 warning generated.

Fix it by using the right format string here.

Message-ID: <20260306203645.28232-1-thuth@redhat.com>
Reviewed-by: Farhan Ali<alifm@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
98c93dfec1 tests/qtest: Add s390x PCI boot test to cdrom-test.c
Add a rudimentary test for s390x IPL to verify that a guest may boot using
virtio-blk-pci device.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-16-jrossi@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
c77da4c0d6 hw: Add "loadparm" property to virtio block PCI devices booting on s390x
The loadparm is required on s390x to pass the information to the boot loader
such as which kernel should be started or whether the boot menu should be shown.

Because PCI devices do not naturally allocate space for this, the property is
added on an architecture specific basis for supported device types.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-15-jrossi@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
395116781d s390x: Build IPLB for virtio-pci devices
Search for a corresponding S390PCIBusDevice and build an IPLB if a device has
been indexed for boot but does not identify as a CCW device,

PCI devices are not yet included in boot probing (they must have a boot index).

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-14-jrossi@linux.ibm.com>
[thuth: Fix endianness issue when running on a little endian host]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
d72fb5e6b2 pc-bios/s390-ccw: Add support for virtio-blk-pci IPL
Add little-endian virt-queue configuration and support for virtio-blk-pci IPL
devices.

Reviewed-by: Eric Farman <farman@linux.ibm.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-13-jrossi@linux.ibm.com>
[thuth: Fix coding style error & spelling warning reported by checkpatch.pl]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
40d80aedd5 pc-bios/s390-ccw: Introduce virtio-pci functions
Define common functionality for interacting with virtio-pci devices.

Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Acked-by: Matthew Rosato <mjrosato@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Message-ID: <20260309003601.242634-12-jrossi@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
5ed17bb32a pc-bios/s390-ccw: Introduce PCI device
Define selected s390x PCI instructions.

Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260309003601.242634-11-jrossi@linux.ibm.com>
Reviewed-by: Farhan Ali <alifm@linux.ibm.com>
[thuth: Remove unused defines as suggested by Farhan]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
284a595c47 s390x: Add definitions for PCI IPL type
Define a new PBT code and IPLB layout in preparation for supporting PCI device
IPL on s390x.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-10-jrossi@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:45 +01:00
Jared Rossi
d3da8afd1d pc-bios/s390-ccw: Introduce CLP Architecture
Call Logical Processor (CLP) Architecture is used for managing PCI functions on
s390x. Define and include the structures and routines needed to interact with
PCI devices during IPL.

Reviewed-by: Eric Farman <farman@linux.ibm.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Reviewed-by: Farhan Ali <alifm@linux.ibm.com>
Message-ID: <20260309003601.242634-9-jrossi@linux.ibm.com>
[thuth: fix a typo in one of the comments]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:46:11 +01:00
Jared Rossi
fa8d22f628 include/hw/s390x: Move CLP definitions for easier BIOS access
Move the s390-pci-clp definitions into the "ipl" sub-directory, which is visible
to the s390-bios.  This allows the bios to reuse the architected definitions and
prevents code duplication.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Signed-off-by: Jared Rossi <jrossi@linux.ibm.com>
Message-ID: <20260309003601.242634-8-jrossi@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2026-03-10 06:36:01 +01:00