Build the 12 per-opcode bit-count tests as a single executable,
test_msa_bit_count.c, to reduce the number of test binaries.
Each opcode reports one TAP line.
Prefix the per-instruction summary of test_utils_128.h with '# '
so TAP parsers treat it as a comment.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20261030175357.99684-16-philmd@oss.qualcomm.com>
Build the 6 per-opcode bitops tests as a single executable,
test_mips64r6_bitops.c, to reduce the number of test binaries.
Each opcode reports one TAP line.
Prefix the per-case output of test_utils_64.h with '# ' so TAP
parsers treat it as a comment.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20261030175357.99684-11-philmd@oss.qualcomm.com>
Build the 19 per-opcode acc tests as a single executable,
test_dsp_acc.c, to reduce the number of test binaries.
Each opcode reports one TAP line.
Add test_dsp_runner.h: assert() only counts failures, and
RUN_TEST() resets DSPControl and reports each test in TAP.
Drop the unused hello-world test.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20261030175357.99684-3-philmd@oss.qualcomm.com>
Add a small header to report test results using the Test Anything
Protocol, which meson parses when the test declares the 'tap'
protocol:
- TAP_START() prints the TAP version line.
- tap_report() prints one numbered "ok" / "not ok" line, with a
printf-style description.
- TAP_CHECK() reports a condition, using its text as description.
- tap_info() prints a printf-style diagnostic line prefixed with '# ',
exposed as TAP_INFO(). It is not a test result: it neither prints a
number nor counts towards the plan or the exit status.
- tap_assert() is a non-fatal assert: it prints a '# FAIL' TAP
diagnostic (via TAP_INFO()) and counts the failure in
tap_assert_failures, for tests grouping several asserts into a
single reported result.
- tap_done() prints the plan and returns the exit status for main().
The counters are static, so each test must be a single translation
unit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20261030174856.98759-2-philmd@oss.qualcomm.com>
Replace runtime helpers by translation.
BE LD.D/ST.D now uses MO_BE with exchanged half handles;
no explicit D swaps or store-copy temporaries.
Replace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st()
which allow to respect atomicity.
Remove the ensure_writable_pages() hack and MSALDST_PROTO macro.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261029151317.19170-6-philmd@oss.qualcomm.com>
helper_msa_ld_d() and helper_msa_st_d() use the legacy
cpu_ldq_data_ra() / cpu_stq_data_ra() accessors, whose endianness
is fixed at build time by TARGET_BIG_ENDIAN. All other MSA load
and store helpers check the vCPU endianness at runtime via
mips_env_is_bigendian().
Do the same for the doubleword variants, so they keep working
when the vCPU endianness differs from the build-time default.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261028180040.22848-6-philmd@oss.qualcomm.com>
Convert LI[16] and LI[48]. LI[16] decodes its 3-bit register
with gpr3() and its immediate with s_eu() (0x7f encodes -1).
LI[48] takes a 32-bit immediate and is not available in NMS
cores; handle it in trans_LI_nnms(), which checks NMS before
calling trans_LI(). Expose check_nms() for that purpose.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261026162034.32711-15-philmd@oss.qualcomm.com>
Convert both the 16-bit RI and the extended EXT-RI forms.
Decode the destination with xlat(); both immediates are
zero-extended (8-bit and 16-bit).
The legacy decoder ignored EXT-RI bits [7:5]; the pattern
requires them to be zero, as specified. Other encodings
now raise a Reserved Instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261026162034.32711-14-philmd@oss.qualcomm.com>
The 3-bit register fields of MIPS16e and microMIPS 16-bit
encodings map to the same 8 GPRs. The map is duplicated,
and we want to re-use it for nanoMIPS. Rename as common
gpr3_m16() helper, using the decodetree !function signature
so both the legacy and the decodetree decoders can call it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261026162034.32711-11-philmd@oss.qualcomm.com>
Call the generic gen_lsa(), using plus_1() to add 1 to
the shift amount. LSA is a Release 6 instruction: add it
to micromips32_r6.decode, which is only called on R6 CPUs.
The legacy decoder only matched bits [5:0]; the pattern
also requires bits [8:6] to be zero, as specified. Other
encodings now raise a Reserved Instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20261026162034.32711-9-philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Add empty decodetree files for the nanoMIPS 16-bit, 32-bit
and 48-bit instructions.
The instruction size is known from the first halfword: 16-bit
major opcodes have bit 12 set, and the P48I major opcode is
the only 48-bit one. Call the matching decoder, reading only
the halfwords needed. Unmatched opcodes fall back to the
legacy decoder.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20261026162034.32711-8-philmd@oss.qualcomm.com>
Add empty decodetree files for the microMIPS 16-bit and 32-bit
instructions, and micromips32_r6.decode for the 32-bit encodings
only valid on Release 6.
Select the 16-bit or 32-bit decoder from the instruction size,
loading the second halfword only for 32-bit instructions. The R6
decoder is only called on R6 CPUs, like decode_isa_rel6() in
decode_opc(), so its patterns need no check_insn(ISA_MIPS_R6).
Unmatched opcodes fall back to the legacy decoder.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20261026162034.32711-6-philmd@oss.qualcomm.com>
Compute whether the instruction is 16-bit or 32-bit unconditionally,
then use the result for the delay slot size check. The default case
is unreachable. No functional change.
The size will be used to select the 16-bit or 32-bit decodetree
decoder in the next commit.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261026162034.32711-5-philmd@oss.qualcomm.com>
Introduce the MIPS16e decodetree configs for the 16-bit
and 32-bit instructions.
EXTEND-prefixed and JAL/JALX instructions are 32-bit, all
others are 16-bit. Call the matching decoder, loading the
second halfword only for 32-bit instructions. Unmatched
opcodes fall back to the legacy decoder.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20261026162034.32711-4-philmd@oss.qualcomm.com>
Historically we were only calling decode_opc() from the MIPS
translate_insn() handler. Then variable instruction length
ISAs were added, we kept using the same pattern but call
yet more translator_ld() in the callees when necessary.
This is cumbersome and bug prone, so better move all
translator_ld() calls to the callees where it is more
logical.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20261026162034.32711-2-philmd@oss.qualcomm.com>
PPC PR for 11.2 Soft Freeze
# -----BEGIN PGP SIGNATURE-----
#
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# j7sIWg/8C1FVTFJYm+gFZs1rb9drL4khMMoy0HcpHvBwDMFtnknK7I6Ul33edLHy
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# J/vDY1gqNKXToIR3lEvwJyJQfWai9n6f/gW6lNBFOa2U6OPK7UBer5vE7OB+RRfV
# 5Sv2Jy/hOu1rWWSFaxrJ+Pw9zuk5iVEKpLJnoYFrDJlbDexUsDZw8YR+Rpkcn64+
# lN4C6BEjb7TaY/pJS7agDQ85SiScDif7/dkG2qV9i0k3RR/YbZEnkbKVhWHzcjIv
# I6eqDTSs11Lb7Xc9DR/xn+Lkt1KfBYZzKYDXqy6veM0hqA1YwD+jT/K+KUMbldFe
# AeI8MPauMVifY5oI2vnXC5dFsr+O7hxAp6raMQci0m6KdUUM1wN5Gz9ghPRdjjyV
# f4C4rPzhpk0dy7X14qccfVVquhz0UFHjwwfwFewg1IoSSvh9vl46FGa1bO+MJGNu
# dJUk0Q2wW/VgJ2S7Dt04SoGlE+PqBLwJoMvnDCQEOmBYZaUI010=
# =rVvI
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 02 Nov 2026 03:13:31 AM PST
# gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
# gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-11.2-sf-20261102' of https://gitlab.com/harshpb/qemu:
pnv/phb5: Mask off LSI Source-ID based on number of interrupts
pnv/phb5: Implement IODA PCT table
pnv/phb5: Set link speed and width in the DLP training control register
pnv/phb5: Set link-active status in HPSTAT and LMR registers
pnv/phb5: Implement write-clear and return 1's on unimplemented reg read
pnv/phb5: Implement read-only and write-only bits of registers
pnv/phb5: Implement sticky reset logic in PHB5
pnv/phb5: Add reset logic to PHB5
qtest/phb5: Add testbench for PHB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
On FreeBSD the virtio-console port is a tty, unlike Linux's
/dev/virtio-ports which is a character device. It defaults to canonical
mode with echo and software flow control enabled, so the QGA stream
protocol does not work: the initial guest-sync handshake is held in the
line discipline and the host eventually times out.
The existing FreeBSD-specific code only clears ECHO. Configure the port
the same way as the ISA serial path: disable canonical mode, echo and
software flow control, and set VMIN/VTIME. Use TCSANOW instead of
TCSAFLUSH so a handshake that arrives between open() and tcsetattr() is
not discarded.
Tested on FreeBSD 15.1 aarch64 under UTM/QEMU. Before the change
utmctl ip-address timed out and the guest received zero bytes; after the
change QGA commands and guest-set-time work.
Cc: qemu-stable@nongnu.org
Fixes: c6cd588bb3 ("qga: Add initial FreeBSD support")
Signed-off-by: Oleksij Samorukov <samm@net-art.cz>
Reviewed-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
Tested-by: Roman Bogorodskiy <bogorodskiy@gmail.com>
Link: https://lore.kernel.org/qemu-devel/20261017201905.12211-1-samm@net-art.cz
Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
