James Hilliard e3c6d52fa0 target/mips: add Octeon CHORD and LLM COP2 helpers ...

Add the Octeon CHORD hardware register access path and the LLM 36-bit
and 64-bit read and write windows. Model both CHORD access forms,
including the RDHWR $30 path and the legacy DMFC2 alias.

Implement sparse backing storage for the two LLM sets so user-mode code
can save, restore, and probe the architectural state without allocating a
full hardware-sized backing array.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-13-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

2026-07-07 20:14:46 +02:00

..

addr.c

…

cp0_timer.c

buildsys: Remove MIPS KVM

2026-05-21 08:20:58 +02:00

cp0.c

…

machine.c

target/mips: add Octeon CHORD and LLM COP2 helpers

2026-07-07 20:14:46 +02:00

meson.build

…

mips-qmp-cmds.c

target/qmp: Use target_cpu_type()

2025-07-15 02:56:39 -04:00

physaddr.c

buildsys: Remove MIPS KVM

2026-05-21 08:20:58 +02:00