starred/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2026-07-08 17:46:10 +00:00
Code Issues 380 Packages Projects Releases Wiki Activity
Files
2c8cf1f16d889bd0dd0806558787816dc4de5359
qemu/target/mips/system/machine.c
James Hilliard e3c6d52fa0 target/mips: add Octeon CHORD and LLM COP2 helpers 
Add the Octeon CHORD hardware register access path and the LLM 36-bit
and 64-bit read and write windows. Model both CHORD access forms,
including the RDHWR $30 path and the legacy DMFC2 alias.

Implement sparse backing storage for the two LLM sets so user-mode code
can save, restore, and probe the architectural state without allocating a
full hardware-sized backing array.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-13-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
2026-07-07 20:14:46 +02:00

496 lines
16 KiB
C
Raw Blame History

#include "qemu/osdep.h"
#include "qemu/target-info.h"
#include "cpu.h"
#include "internal.h"
#include "migration/cpu.h"
#include "migration/qemu-file-types.h"
#include "fpu_helper.h"
#include "qemu/timer.h"
static int cpu_post_load(void *opaque, int version_id)
{
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
restore_fp_status(env);
restore_msa_fp_status(env);
compute_hflags(env);
restore_pamask(env);
return 0;
}
/* FPU state */
static int get_fpr(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
int i;
fpr_t *v = pv;
/* Restore entire MSA vector register */
for (i = 0; i < MSA_WRLEN / 64; i++) {
qemu_get_sbe64s(f, &v->wr.d[i]);
}
return 0;
}
static int put_fpr(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
int i;
fpr_t *v = pv;
/* Save entire MSA vector register */
for (i = 0; i < MSA_WRLEN / 64; i++) {
qemu_put_sbe64s(f, &v->wr.d[i]);
}
return 0;
}
static const VMStateInfo vmstate_info_fpr = {
.name = "fpr",
.get = get_fpr,
.put = put_fpr,
};
#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
static const VMStateField vmstate_fpu_fields[] = {
VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
VMSTATE_END_OF_LIST()
};
static const VMStateDescription vmstate_fpu = {
.name = "cpu/fpu",
.version_id = 1,
.minimum_version_id = 1,
.fields = vmstate_fpu_fields
};
static const VMStateDescription vmstate_inactive_fpu = {
.name = "cpu/inactive_fpu",
.version_id = 1,
.minimum_version_id = 1,
.fields = vmstate_fpu_fields
};
/* TC state */
static const VMStateField vmstate_tc_fields[] = {
VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
#if defined(TARGET_MIPS64)
VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32),
#endif /* TARGET_MIPS64 */
VMSTATE_UINTTL(PC, TCState),
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL(DSPControl, TCState),
VMSTATE_INT32(CP0_TCStatus, TCState),
VMSTATE_INT32(CP0_TCBind, TCState),
VMSTATE_UINTTL(CP0_TCHalt, TCState),
VMSTATE_UINTTL(CP0_TCContext, TCState),
VMSTATE_UINTTL(CP0_TCSchedule, TCState),
VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
VMSTATE_UINTTL(CP0_UserLocal, TCState),
VMSTATE_INT32(msacsr, TCState),
VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1),
VMSTATE_UINTTL(mxu_cr, TCState),
VMSTATE_END_OF_LIST()
};
static const VMStateDescription vmstate_tc = {
.name = "cpu/tc",
.version_id = 2,
.minimum_version_id = 2,
.fields = vmstate_tc_fields
};
static const VMStateDescription vmstate_inactive_tc = {
.name = "cpu/inactive_tc",
.version_id = 2,
.minimum_version_id = 2,
.fields = vmstate_tc_fields
};
static const VMStateDescription vmstate_octeon_multiplier_tc = {
.name = "cpu/tc/octeon_multiplier",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT64_ARRAY(octeon.MPL, TCState, OCTEON_MULTIPLIER_REGS),
VMSTATE_UINT64_ARRAY(octeon.P, TCState, OCTEON_MULTIPLIER_REGS),
VMSTATE_END_OF_LIST()
}
};
typedef struct OcteonLLMTreePutData {
QEMUFile *f;
} OcteonLLMTreePutData;
static gboolean put_octeon_llm_tree_entry(gpointer key, gpointer value,
gpointer user_data)
{
OcteonLLMTreePutData *data = user_data;
qemu_put_be64(data->f, *(uint64_t *)key);
qemu_put_be64(data->f, *(uint64_t *)value);
return false;
}
static int put_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
QTree *tree = *(QTree **)pv;
OcteonLLMTreePutData data = { .f = f };
uint32_t nnodes = tree ? q_tree_nnodes(tree) : 0;
qemu_put_be32(f, nnodes);
if (tree) {
q_tree_foreach(tree, put_octeon_llm_tree_entry, &data);
}
return 0;
}
static int get_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
QTree **treep = pv;
uint32_t nnodes = qemu_get_be32(f);
if (*treep) {
q_tree_destroy(*treep);
}
*treep = mips_octeon_llm_tree_new();
for (uint32_t i = 0; i < nnodes; i++) {
uint64_t addr = qemu_get_be64(f);
uint64_t value = qemu_get_be64(f);
mips_octeon_llm_store(treep, addr, value);
}
return 0;
}
static const VMStateInfo vmstate_info_octeon_llm_tree = {
.name = "octeon_llm_tree",
.get = get_octeon_llm_tree,
.put = put_octeon_llm_tree,
};
#define VMSTATE_OCTEON_LLM_TREE(_f, _s) { \
.name = stringify(_f), \
.version_id = 1, \
.info = &vmstate_info_octeon_llm_tree, \
.offset = vmstate_offset_pointer(_s, _f, QTree), \
}
/* MVP state */
static const VMStateDescription vmstate_mvp = {
.name = "cpu/mvp",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
VMSTATE_END_OF_LIST()
}
};
/* TLB state */
static int get_tlb(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
r4k_tlb_t *v = pv;
uint16_t flags;
if (target_long_bits() == 64) {
v->VPN = qemu_get_be64(f);
} else {
v->VPN = qemu_get_be32(f);
}
qemu_get_be32s(f, &v->PageMask);
qemu_get_be16s(f, &v->ASID);
qemu_get_be32s(f, &v->MMID);
qemu_get_be16s(f, &flags);
v->G = (flags >> 10) & 1;
v->C0 = (flags >> 7) & 3;
v->C1 = (flags >> 4) & 3;
v->V0 = (flags >> 3) & 1;
v->V1 = (flags >> 2) & 1;
v->D0 = (flags >> 1) & 1;
v->D1 = (flags >> 0) & 1;
v->EHINV = (flags >> 15) & 1;
v->RI1 = (flags >> 14) & 1;
v->RI0 = (flags >> 13) & 1;
v->XI1 = (flags >> 12) & 1;
v->XI0 = (flags >> 11) & 1;
qemu_get_be64s(f, &v->PFN[0]);
qemu_get_be64s(f, &v->PFN[1]);
return 0;
}
static int put_tlb(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
r4k_tlb_t *v = pv;
uint16_t asid = v->ASID;
uint32_t mmid = v->MMID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
(v->XI1 << 12) |
(v->XI0 << 11) |
(v->G << 10) |
(v->C0 << 7) |
(v->C1 << 4) |
(v->V0 << 3) |
(v->V1 << 2) |
(v->D0 << 1) |
(v->D1 << 0));
if (target_long_bits() == 64) {
qemu_put_be64(f, v->VPN);
} else {
qemu_put_be32(f, v->VPN);
}
qemu_put_be32s(f, &v->PageMask);
qemu_put_be16s(f, &asid);
qemu_put_be32s(f, &mmid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
return 0;
}
static const VMStateInfo vmstate_info_tlb = {
.name = "tlb_entry",
.get = get_tlb,
.put = put_tlb,
};
#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
static const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
.version_id = 3,
.minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
VMSTATE_END_OF_LIST()
}
};
/* MIPS CPU state */
static bool mips_timer_needed(void *opaque)
{
MIPSCPU *cpu = opaque;
return cpu->env.timer != NULL;
}
static const VMStateDescription mips_vmstate_timer = {
.name = "cpu/timer",
.version_id = 1,
.minimum_version_id = 1,
.needed = mips_timer_needed,
.fields = (const VMStateField[]) {
VMSTATE_TIMER_PTR(env.timer, MIPSCPU),
VMSTATE_END_OF_LIST()
}
};
static bool mips_octeon_needed(void *opaque)
{
MIPSCPU *cpu = opaque;
return cpu->env.insn_flags & INSN_OCTEON;
}
static const VMStateDescription mips_vmstate_octeon_multiplier = {
.name = "cpu/octeon_multiplier",
.version_id = 1,
.minimum_version_id = 1,
.needed = mips_octeon_needed,
.fields = (const VMStateField[]) {
VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1,
vmstate_octeon_multiplier_tc, TCState),
VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
vmstate_octeon_multiplier_tc, TCState),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription mips_vmstate_octeon_crypto = {
.name = "cpu/octeon_crypto",
.version_id = 1,
.minimum_version_id = 1,
.needed = mips_octeon_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8),
VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3),
VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU),
VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4),
VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU),
VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2),
VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU),
VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU),
VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU),
VMSTATE_UINT64(env.octeon_crypto.chord, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.llm_data, MIPSCPU, 2),
VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm36, MIPSCPU),
VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm64, MIPSCPU),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
.version_id = 21,
.minimum_version_id = 21,
.post_load = cpu_post_load,
.fields = (const VMStateField[]) {
/* Active TC */
VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
/* Active FPU */
VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
CPUMIPSFPUContext),
/* MVP */
VMSTATE_STRUCT_POINTER(mvp, MIPSCPU, vmstate_mvp,
CPUMIPSMVPContext),
/* TLB */
VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
CPUMIPSTLBContext),
/* CPU metastate */
VMSTATE_UINT32(env.current_tc, MIPSCPU),
VMSTATE_UNUSED(sizeof(uint32_t)), /* was current_fpu */
VMSTATE_INT32(env.error_code, MIPSCPU),
VMSTATE_UINTTL(env.btarget, MIPSCPU),
VMSTATE_UINTTL(env.bcond, MIPSCPU),
/* Remaining CP0 registers */
VMSTATE_INT32(env.CP0_Index, MIPSCPU),
VMSTATE_INT32(env.CP0_VPControl, MIPSCPU),
VMSTATE_INT32(env.CP0_Random, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */
VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU),
VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
VMSTATE_INT32(env.CP0_Config4, MIPSCPU),
VMSTATE_INT32(env.CP0_Config5, MIPSCPU),
VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
VMSTATE_UINTTL(env.lladdr, MIPSCPU),
VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU),
VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
/* Inactive TC */
VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
vmstate_inactive_tc, TCState),
VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
vmstate_inactive_fpu, CPUMIPSFPUContext),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
&mips_vmstate_timer,
&mips_vmstate_octeon_multiplier,
&mips_vmstate_octeon_crypto,
NULL
}
};
Reference in New Issue View Git Blame Copy Permalink