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Prepare the Aspeed SoC model for future platforms that may contain multiple SRAM regions with different sizes and MMIO mappings. The current implementation stores SRAM size information in a single sram_size field, which limits extensibility when additional SRAM instances are introduced. Convert sram_size into an array-based definition and update all existing users to reference sram_size[0]. This aligns with the previous SRAM MemoryRegion array conversion and provides a scalable foundation for supporting multiple SRAM regions in future SoCs. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>