mirror of
https://github.com/qemu/qemu.git
synced 2026-11-12 14:50:50 +00:00
4700a316df7d2cdcd256dcd64a10cec643f4dfa1
The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
…
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
Description
Languages
C
83.4%
C++
6%
Python
3.5%
Dylan
2.7%
Shell
1.2%
Other
3%