Files
qemu/include/hw/intc
Peter Maydell 9ec3a7a53c target/arm: GICv5 cpuif: Don't set HPPIV bit in GICv5PendingIrq::intid
In gic_hppi() we return the current highest priority pending
interrupt in a GICv5PendingIrq struct.  We try to set up the intid
field of that struct to be the form that is used by the ICC_HPPIR
register, which has a "valid" bit in bit 33.  Unfortunately the
GICv5PendingIrq defines the intid field as a uint32_t, so Coverity
points out that the bit doesn't actually fit.  Move the handling of
the valid bit to the callsite, and make this function report "no
pending interrupt" with GICv5PendingIrq::prio == PRIO_IDLE,
consistently with how we use this struct in other places.

CID: 1659594
Fixes: 9edad4ff3 ("target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260512093856.3197700-3-peter.maydell@linaro.org
2026-05-15 09:47:22 +01:00
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2023-02-27 22:29:01 +01:00
2025-12-27 10:11:08 +01:00