Files
qemu/hw/core
Stefan Hajnoczi 0951d6dab1 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386/mshv: CPU model support
* target/i386/mshv: first part of migration support
* target/i386/mshv: faster register access for MMIO exits
* target/i386/tdx: add support for AMX alias bits in CPUID and AVX10
* Deprecate memory-encryption in favor of confidential-guest-support

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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (45 commits)
  i386/tdx: Add CPUID_24_0_EBX_AVX10_VL_MASK as supported
  i386/tdx: Make AMX alias bits supported
  i386/tdx: Use .has_gpa field to check if the gpa is valid
  machine: Deprecate memory-encryption
  qemu-options: Add description of tdx-guest object
  qemu-options: Add confidential-guest-support to machine options
  qemu-options: Change memory-encryption to confidential-guest-support in the example
  i386/sev: Remove the example that references memory-encryption
  target/i386/mshv: use the register page to set registers
  target/i386/mshv: use the register page to get registers
  target/i386/mshv: hv_vp_register_page setup for the vcpu
  include/hw/hyperv: add hv_vp_register_page struct definition
  accel: remove unnecessary #ifdefs
  target/i386/mshv: migrate CET/SS MSRs
  target/i386/mshv: migrate MTRR MSRs
  target/i386/mshv: migrate MSRs
  target/i386/mshv: reconstruct hflags after load
  target/i386/mshv: migrate XSAVE state
  target/i386/mshv: migrate pending ints/excs
  target/i386/mshv: move msr code to arch
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2026-06-27 23:06:04 -04:00
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