mirror of
https://github.com/qemu/qemu.git
synced 2026-10-28 23:52:46 +00:00
d9f4bb27dbff2e40ec2e36eb8017c9dedce77f30
This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Read the documentation in qemu-doc.html. Fabrice Bellard.
Description
Languages
C
83.3%
C++
6%
Python
3.5%
Dylan
2.7%
Shell
1.2%
Other
3.1%