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RISC-V PR for 11.1. * Remove spike as default machine * Deprecate the shakti_c machine * Set MISA.[C|X] based on the selected extensions * Update Maintainers for OpenSBI Firmware * Update OpenSBI to v1.8.1 * Avoid RISCVCPU copy in PMU FDT setup * A collection of specification compliance improvements * Fix Svnapot 64KB pages * Handle source overlap of vector widening reduction instructions * Check interrupt in SiFive UART after txctrl register is written * Fix medeleg[11] read-only zero bit for M-mode ECALL * Fix tail handling for vmv.s.x and vfmv.s.f * Update the local AIA interrupt mask * Add KVM support for Zicbop and BFloat16 extensions * Fix the IOMMU FSC SV32 capability check * Avoid caching PCI device IDs in the IOMMU * Implement Microchip mpfs ioscb PLLs and sysreg clock dividers * Remove the internal CPU riscv_cpu_* arrays * Fix IOCOUNTINH.CY toggle detection * Fix the read of pmpaddr(0-63) CSRs * Make hpmcounterh return the upper 32-bits * Minor fixes and enhancements of RISC-V AIA devices * Re-process IOMMU command queue after clearing CMD_ILL # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmoPnQkACgkQr3yVEwxT # gBMudxAAvN8XD1zauMzk62tkXCmVA5fjqtTqu4Ytp8Pe3P7ZX9FZP6Alcw+G+zEd # QQdIeHTzxzs77LO5VLKlLS807W5by9eMQDPOWvCRk2rQWJfgbxYq//dJNOPpJfR1 # ptDsvnxonfn8lh34Bm7nI+UaznRVSr3mSts8LN5R9GANLHRPYbJbtSRb2qSGBPzP # ynNvuD0tmt9gXf+j9O9qr5DkoRoiZdoRTGdQ9a/eWlxP/eNvPzq0c74ToPpz3Obv # 6z/ICImKZGL36W8B73FbGy30EySihdPTcLSQHqsUZ+mYtj+6WGtIbIoZkaugnfml # M8DuukT6sO8GdZy7cFnxhThsnZ+HEylzpjHHWYJlvY9uUniM0wrCavCc0lvUm71A # Mi0yASlmv6kXotxtmz+UZF6/h7vTJHXvEo/g9cwshSVjxYDhHf8GtIYVegLTTeoP # z1UfpdepH6fe9E8cf6DUSwr1syODSf0qjiKVMVMxb/OMEk3qEB0uwbG+X1Ecs9s1 # SQo6cp5TdiSjzP87MyMDeTeaS6FQrkVEkXXgcpFf1W/R0zRuj/JW89sGCJvS7Tqk # +bH4pNnzXTBNxuGrb3zZSC0yWdroSiqyT+9g/JlQMY9tBvnoY8p7Ck7g07nLhVSf # Cj4C0SXRMSj8eHn2+pDqjZn1RUfG2mRAD+8yYWqZ2GvU2X/yhx8= # =SSwl # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 May 2026 20:02:17 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu: (48 commits) hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL hw/intc: riscv_aplic: add trace events of APLIC read/write function hw/intc: riscv_imsic: Add reset API to IMSIC hw/intc: riscv_aplic: Add reset API to APLIC hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode target/riscv: Make hpmcounterh return the upper 32-bits hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection target/riscv/cpu: remove riscv_cpu_* arrays target/riscv/tcg: use isa_edata_arr[] to create user props target/riscv: do not set defaults in cpu prop callback target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque target/riscv/tcg: use isa_edata_arr[] to enable max exts target/riscv/kvm: use isa_edata_arr[] for unavailable props target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x() target/riscv: remove riscv_cpu_named_features[] target/riscv/cpu.c: remove riscv_cpu_enable_named_feat() target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name() target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>