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83fb4955f2edea0de0df2e3e1e9a562ecde423ed
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Author SHA1 Message Date
Natalia Portillo
83fb4955f2 Add AVX2 implementation of CRC16-IBM. 2025-08-21 00:58:51 +01:00
Natalia Portillo
b8a97a8a05 Add PCLMUL implementation of CRC16-CCITT. 2025-08-21 00:22:17 +01:00
Natalia Portillo
2e857b0240 Update copyright year. 2024-12-19 15:21:40 +00:00
Natalia Portillo
dfdb2990e4 Update IntelliJ project files. 2024-12-19 15:20:24 +00:00
Natalia Portillo
5136cb7540 Udpate editorconfig file. 2024-12-19 15:19:42 +00:00
Natalia Portillo
bd5051ce18 General refactor and cleanup. 2024-04-30 15:12:48 +01:00
Natalia Portillo
552aa9da02 Up version to 6.0.0-alpha.10 2024-04-30 15:12:12 +01:00
Natalia Portillo
efec9272d7 Update build script for WoA targets. 2024-04-30 15:11:51 +01:00
Natalia Portillo
465830408c Add codealike.json. 2024-04-30 15:11:17 +01:00
Natalia Portillo
e9b4aa70b9 Update editorconfig and clang-format files. 2024-04-30 15:10:50 +01:00
Natalia Portillo
31edfa0758 Enable optimizations. 2023-09-24 20:20:43 +01:00
Natalia Portillo
0d9d1d92eb Fix Adler and Fletcher calculations using SIMD when dataset is smaller than block size. 2023-09-24 19:33:25 +01:00
JosJuice
89382334ec Implement Fletcher-16 using AVX2 instructions 2023-09-24 18:46:45 +01:00
JosJuice
712281aba5 Implement Fletcher-16 using ARM NEON instructions 2023-09-24 18:46:45 +01:00
JosJuice
2878dea20d Implement Fletcher-16 using SSSE3 instructions 2023-09-24 18:46:45 +01:00
JosJuice
a9b6c4868b Expand Fletcher-16 NMAX 
The limit when calculating the value of NMAX is 2^16-1 only when sum1
and sum2 are represented as 16-bit. We're representing them as 32-bit.

This will be helpful for SIMD implementations of Fletcher-16, because
the old limit of 22 bytes would have meant that we could only process
16 bytes at a time before having to compute modulo.
 2023-09-24 18:46:45 +01:00
JosJuice
449c25012d Add Fletcher-16 tests for small lengths 
To prevent the bug fixed in the previous commit from reoccuring.
 2023-09-24 18:46:45 +01:00
JosJuice
d6d1c8dae5 Fix Fletcher-16 for small lengths 
For Fletcher-32, the conditional subtract approach works for lengths up
to 514 bytes, but for Fletcher-16 it only works up to 2 bytes due to
FLETCHER16_MODULE being much smaller than FLETCHER32_MODULE.
 2023-09-24 18:46:45 +01:00
Natalia Portillo
d325d82cf1 Fix TARGET_WITH in wrong places. 2023-09-23 19:51:50 +01:00
Natalia Portillo
0bcfa9c5e5 Add shareable IntelliJ project files. 2023-09-23 19:18:49 +01:00
Natalia Portillo
1905cb0d43 Refactor and reformat. 2023-09-23 18:55:52 +01:00
Natalia Portillo
33f021fd54 Add documentation. 2023-09-23 18:10:44 +01:00
Natalia Portillo
3358d66f0a Implement Fletcher-32 using AVX2 instructions. 2023-09-23 03:12:46 +01:00
Natalia Portillo
ccf605367d Implement Fletcher-32 using SSSE3 instructions. 2023-09-23 02:51:57 +01:00
Natalia Portillo
b3ef2a3188 Add test for Fletcher-32 using ARM NEON instructions. 2023-09-23 02:48:12 +01:00
Natalia Portillo
6bfd6c7c83 Implement Fletcher-32 using ARM NEON instructions. 2023-09-23 02:44:19 +01:00
Natalia Portillo
1bd06bb761 Enable ADLER32 using NEON in 32-bit Windows on ARM. 2023-09-23 01:34:29 +01:00
Natalia Portillo
e18fe4d973 Enable ARM CRC32 test in ARMv7 compilers. 2023-09-23 01:01:59 +01:00
Natalia Portillo
5ab52989c1 Fix declaration of ARM CRC32 function in ARMv7 compilers. 2023-09-23 01:01:41 +01:00
Natalia Portillo
d4a607345e Lower ARM architecture requirement for CRC32 instructions. 
The changes ensure compatibility with compilers targeting ARMv7.
32-bit processors of architecture 8 and higher, or 64-bit processors running in 32-bit mode can have the CRC32 instructions.
With this change we will query the processor instead of the compiler architecture.
 2023-09-23 00:53:23 +01:00
Natalia Portillo
c392dfa682 Fixed typo in ARM32 CRC32 instruction call. 2023-09-23 00:50:37 +01:00
Natalia Portillo
27cabe4c48 Allow ADLER32 using NEON instructions to be used in Visual C++ compiler. 2023-09-23 00:49:50 +01:00
Natalia Portillo
a08fc98bc8 Fix detection of CRC32 opcodes in Apple Silicon. 2022-12-02 22:29:14 +00:00
Natalia Portillo
722d910bbb Up version to 6.0.0-alpha9. 2022-12-01 23:07:49 +00:00
Natalia Portillo
fa8a32096c Disable building linux-musl-arm as it is not working anymore. 2022-12-01 23:07:34 +00:00
Natalia Portillo
765ebaf40a Add build for linux-ppc64le. 2022-12-01 23:07:04 +00:00
Natalia Portillo
a7282867e4 Change build of linux-armv7a to LTS so it requires a lower version of glibc. 2022-12-01 23:06:50 +00:00
Natalia Portillo
7e9f26e2df Update copyright year. 2022-12-01 23:06:20 +00:00
Natalia Portillo
149b1492d9 Add detection of MSVC for ARM64 in vmull. 2022-12-01 22:11:50 +00:00
Natalia Portillo
f575fd2d08 Add README. 2021-10-31 17:39:48 +00:00
Natalia Portillo
b327568704 Create docker directory if not exists. 2021-10-14 04:39:46 +01:00
Natalia Portillo
0c0a4850e5 Ensure MingW32 arm compilations have the inlines for crc32 operations. 2021-10-13 21:06:53 +01:00
Natalia Portillo
4e355fbc3c Separate fixes for MSVC from MingW32. 2021-10-13 21:06:33 +01:00
Natalia Portillo
d950b8fa51 Fix typo in cmake file. 2021-10-13 21:05:59 +01:00
Natalia Portillo
6493e9bda8 Do not build tests from build script. 2021-10-13 21:05:18 +01:00
Natalia Portillo
0ac6d8dd24 Guard mac compilation for Mac OS X only. 2021-10-13 14:32:45 +01:00
Natalia Portillo
a7a822432e Fix cross building for WoA. 2021-10-13 14:31:19 +01:00
Natalia Portillo
b74ecb13d6 Update build script with working architectures. 2021-10-13 05:17:03 +01:00
Natalia Portillo
0184752a9f Add missing include files for simd. 2021-10-13 05:16:52 +01:00
Natalia Portillo
02801c919a Fix compilation in release using Apple's clang. 2021-10-13 05:16:20 +01:00