AMD K6-2 onwards: EFER write GPF is now correctly on bits 5 onwards, not on bits 1 onwards.
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@@ -3705,7 +3705,7 @@ cpu_WRMSR(void)
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/* Extended Feature Enable Register */
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case 0xc0000080:
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temp = EAX | ((uint64_t) EDX << 32);
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if (temp & ~1ULL)
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if (temp & ~0x1fULL)
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x86gpf(NULL, 0);
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else
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msr.amd_efer = temp;
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