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c6dfd688f4dd8516e611b388fc5c53740deddefd
Commit Graph

194 Commits

Author SHA1 Message Date
pankozaC++
6362351987 bring back the Slot 1 to Socket 8 adapter 2025-02-13 19:14:36 +01:00
OBattler
34e3f6e849 No longer list Socket 8 CPU's for Slot 1 machines, closes #5196. 2025-02-07 23:34:12 +01:00
Adrian Siekierka
eb25bccf1e Add initial Mazovia 1016 emulation 2024-12-22 13:52:25 +01:00
OBattler
8f25851406 Pentium II: Change BIOS update signature to non-zero on CPUID with EAX = 1, fixes microcode update error messages on some BIOS'es. 2024-12-22 04:09:55 +01:00
Alexander Babikov
f1a60d8242 Add PSE-36 (36-bit page size extension) support 
Code ported from PCBox
 2024-12-21 20:44:31 +05:00
OBattler
cc8cfb7b3f The CPL checks introduced in build 6212 need to only be made in protected mode, fixes the Daewoo CB52X-SI. 2024-12-03 17:48:07 +01:00
OBattler
0a3f1e3279 RDMSR, WRMSR, and WBINVD now correctly GPF when CPL > 0, fixes #4887. 2024-10-15 23:54:57 +02:00
OBattler
8899b1411b AMD K6-2 onwards: EFER write GPF is now correctly on bits 5 onwards, not on bits 1 onwards. 2024-10-01 09:56:40 +02:00
OBattler
7e0c6e9b69 Enable the SYSENTER/SYSEXIT MSR's on Pentium Pro, fixes OpenBSD booting, fixes #4873. 2024-09-30 18:08:05 +02:00
OBattler
fb3b46f648 Unbroke SCO Xenix on the 286/386 interpreter, this will do until the prefetch queue is finally implemented. 2024-08-29 01:57:22 +02:00
OBattler
7c7cc921ee Non-808x interpreters: fetch the next instruction after a CR0 paging bit toggle with the old CR0 paging bit value, fixes SCO Unix. 2024-08-27 02:34:59 +02:00
Jasmine Iwanek
025798c832 PGE for K5 2024-08-25 20:20:21 -04:00
Jasmine Iwanek
97f861b0ba Split off AMD K5 from K6 2024-08-25 19:08:30 -04:00
Jasmine Iwanek
892f066ffa Don't depend on DEV_BRANCH 
Allows things to be compiled independently
 2024-08-08 20:25:03 -04:00
Cacodemon345
2b3d3ad5bd Make sure timers don't go completely out of sync upon altering TSC via WRMSR 2024-06-18 20:21:23 +06:00
OBattler
a369bc2d05 Reimplement S3 ViRGE reset and move PCI TRC CPU reset to outside the recompiled block, fixes #2903. 2024-06-12 20:46:27 +02:00
OBattler
2273f563a5 Moved the offending SoftFloat-related stuff to x87_sf.h, fixes warnings. 2024-06-10 00:08:48 +02:00
Alexander Babikov
a07ffdecab Restore the debug register operation on 486+ 
But put it behind a compile-time option due to performance hits
Also add the DE flag to CPUID on supported CPUs
 2024-05-24 03:35:08 +05:00
Miran Grča
8928f5d771 Variable to override the 286/386 interpreter. 2024-04-25 19:10:40 +02:00
OBattler
15e3876e21 Prepare WD76C10 for 286/386 interpreter selection, exempt IBM 486BL and all Cyrix'es from the 286/386 interpreter. 2024-04-24 06:06:09 +02:00
Alexander Babikov
996769095b Implement most missing P6 MSRs 
Remove the 6 extraneous performance counter MSRs which
haven't existed on P6
 2024-02-07 12:31:43 +05:00
Alexander Babikov
e54b57641c Implement missing IBM, AMD and Cyrix MSRs 2024-02-07 12:31:42 +05:00
Alexander Babikov
65f40ca71d Implement missing WinChip C6/2 and Cyrix III MSRs 2024-02-07 12:31:42 +05:00
Alexander Babikov
1b9bf568f2 Implement missing Pentium MSRs 
Includes obscure behavior, like undocumented "high" MSRs
 2024-02-07 12:31:41 +05:00
Alexander Babikov
2a3d13d306 Various consistency changes 2024-02-07 12:31:39 +05:00
Alexander Babikov
1e4455d98c Add comments with MSR and CPUID flag names 
Reorganize the MSR struct
 2024-02-07 12:31:38 +05:00
Alexander Babikov
1bb31f3937 Remove the AP61 hack completely 
It's no longer needed
 2024-02-07 12:31:37 +05:00
Alexander Babikov
963525ff2e Correct the CPUID SEP bit on AMD K6-2 and later 
They use the standard bit 11, not he AMD-specific bit 10
 2024-02-07 12:31:37 +05:00
Alexander Babikov
aef257378e Add PGE to AMD K5 and K6-2C/III/2+/III+ 2024-02-07 12:31:36 +05:00
Alexander Babikov
37cf0b6845 Separate Pentium and Cx6x86 MSR handling 2024-02-07 12:31:35 +05:00
Alexander Babikov
a1540eee92 Remove the machine check CPUID flag from the P24T 2024-02-07 12:31:35 +05:00
Alexander Babikov
032a161c4a Implement IDT/VIA FCR2 CPUID family/model spoofing 2024-02-07 12:31:34 +05:00
Alexander Babikov
2da7b196ac Rename unnamed MSR vars to real names where known 2024-02-07 12:31:34 +05:00
OBattler
0a5d25fdde Memory: Disable _mem_exec in phys() accesses when not using the 486+ interpreter or dynamic recompiler, and write protect support in preparation for the WD76C10 rewrite. 2024-02-02 05:25:40 +01:00
OBattler
9107c2fa25 Added the AOpen AP61 and fixed floppies on the LG IBM 440 FX. 2024-01-24 04:56:31 +01:00
OBattler
bd2ef6855a A CPU change in preparation for the AOpen AP61. 2024-01-21 20:21:52 +01:00
OBattler
937e2a52f8 SiS 5571, Daewoo Compaq, speed up AT / PS/2 KBC (does not appear to break anything from months of testing) and fix AT / PS/2 keyboard reset to fix the Samsung SPC7700LP-W soft reset. 2024-01-06 01:51:20 +01:00
RichardG867
61ec3213c6 Merge branch 'master' of ssh://github.com/86Box/86Box into version/4.1 2023-11-07 21:28:51 -03:00
OBattler
7dd13b704c Fixed a compile-breaking mistake in cpu/cpu.c. 2023-11-06 06:51:44 +01:00
Alexander Babikov
8b741d511e Add Page Global Enable feature (toggleable by an MSR) to the Cyrix III 2023-11-06 10:27:27 +05:00
Alexander Babikov
b0b857a50e Don't set Centaur/VIA Feature Control Register MSR on CPUs that lack it 2023-11-06 10:27:24 +05:00
OBattler
09d2f7517c Some CPU fixes. 2023-11-06 06:07:43 +01:00
Alexander Babikov
8f4fe2f9e2 Reorder and reformat comments 2023-11-05 07:20:35 +05:00
Alexander Babikov
33b6166896 Fix the Pentium Pro L1 cache amount 2023-11-05 07:08:33 +05:00
Alexander Babikov
73714e8130 Report correct cache info in CPUID on P6-family CPUs 2023-11-04 10:54:51 +05:00
Jasmine Iwanek
f6a5229a98 Future support for higher clocked CPU's 2023-10-13 17:55:18 -04:00
OBattler
be4d160024 Fixed the state of the 486 DX2 WB CPU's used by the PC 330. 2023-10-13 06:00:38 +02:00
OBattler
1d48363803 The 286/386 interpreter now has its own variant of x86seg.c. 2023-08-21 02:56:33 +02:00
Jasmine Iwanek
5cd18f3fbb Clang-formatting in src/cpu 2023-08-11 19:11:37 -04:00
Jasmine Iwanek
be79ea78c7 sonarlinting and formatting in src/cpu 2023-08-11 19:11:32 -04:00