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amd-gpu: memory barrier additions in MMU code to ensure pagetables are posted

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Matt Sealey
2012-12-10 18:56:25 -06:00
parent fbbe86a046
commit e98a2a565a
1 changed files with 4 additions and 0 deletions
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4
drivers/mxc/amd-gpu/gsl_mmu.c
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@@ -653,6 +653,8 @@ kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *sca
KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map"));
}
mb();
if (flushtlb)
{
// every device's tlb needs to be flushed because the current page table is shared among all devices
@@ -782,6 +784,8 @@ kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pi
status = GSL_FAILURE;
}
mb();
// invalidate tlb, debug only
KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid));