This patch avoids TVE custom suspend/resume functions to be called.
Signed-off-by: Liu Ying <b17645@freescale.com>
(cherry picked from commit ec197f61d6dcc21393ab8ea3ffc5fe071914ccf2)
In function of gadget unregister the phy will been put to lowpower
mode,however in function of gadget regisger the phy lowpower mode will
not been cleard when OTG pin detect enabled.
Signed-off-by: Huhui <b29976@freescale.com>
(cherry picked from commit 11dc51645fe5a196f53fb30369698b4cb4d1e296)
The mmap policy should be writethrough.
Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit aceea32a54b8aa248d771b589d46ce8fbe3c2806)
Change LDB related video mode names to align with MSL
code change.
Signed-off-by: Liu Ying <b17645@freescale.com>
(cherry picked from commit 4356737e33c837d038b99b9c77e1a3310f162e19)
Make LDB related video mode names be common names because the
video names may be used by other devices besides LVDS panels.
Signed-off-by: Liu Ying <b17645@freescale.com>
(cherry picked from commit 65ff4bdb388474875d2111b412c6375e0d1ce0c2)
This patch avoids LDB framebuffer cause black flash issue or potential
black flash issue on one other framebuffer device which connects with
the same di when the system boots up or video mode is changed.
Signed-off-by: Liu Ying <b17645@freescale.com>
(cherry picked from commit b24e782a16b6b5d02f04c8daa7c5ef13f3b05270)
This patch avoids TVE framebuffer cause black flash issue or potential
black flash issue on one other framebuffer device which connects with
the same di when the system boots up or video mode is changed.
Signed-off-by: Liu Ying <b17645@freescale.com>
(cherry picked from commit a5dd4501783ee62c22a16e1d089803e3b1c09944)
memstore should be freed properly. a following change will be prepared to
improve the alloc/free logic for device memstore.
Signed-off-by: Jie Zhou <b30303@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
Adjust the Target dll value to support the TOSHIBA eMMC44 card.
Make sure that IPG, HLK, PER are enabled, and SDCLK is disabled.
SDCLKFS can't be set to zero on esdhc V3 IP.
Signed-off-by: Richard Zhu <r65037@freescale.com>
Use the platform_device_unregister instead of platform_device_put,
to remove the device from the audio subsystem, when it fails to reigster
the cs42888 card.
Signed-off-by: William Lai<b04597@freescale.com>
(cherry picked from commit b096820108269d4d67b44fd8652c475263ee8a18)
If set both double buffer ready for VDI case, there will come out
NFB4EOF error.
Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit 24c1d799767732a7d654c1acd526c63acbe397fe)
Change pgprot_noncached to pgprot_writecombine in gsl_kmod_mmap to
improve performance
Signed-off-by: Thomas Peng <r80085@freescale.com>
Signed-off-by: Jie Zhou <b30303@freescale.com>
(cherry picked from commit 847baca41bceed49e397eaba8b1b3b00e86e20a3)
Judge the codec memeber of the snd_soc_card_imx_3stack after the
platform_device_add function, as only after this function, the
cs42888_codec pointer will be passed to.
Signed-off-by: William Lai <b04597@freescale.com>
There would be a small silent stop in the audio playback
when insert the cards into the slot during the audio playback.
The root cause is the mis-spell delay that would be 10 times larger
than expection. Change the delay back to original expection.
Signed-off-by: Richard Zhu <r65037@freescale.com>
With latest VG/GL fix integration from RC16/EA, there will be some problems
as below, which can be solved by this patch:
- ENGR00124884 will happen again
- suspend/resume will not be supported in gpu driver
Signed-off-by: Jie Zhou <b30303@freescale.com>
Clk tree make default di1_clk's parent clk as pll3 when tve clk disable,
ipu disp module will re-calculate ipu pixel clk if di clk's parent clk
is not tve_clk. If blanks tve-fb0, di1 clk's parent will set to pll3,
unblank tve-fb0 need re-calculate tve clk.
Signed-off-by: Jason Chen <b02280@freescale.com>
If do input right-side crop and input/output are in the same size, v4l2
driver will enable ic_bypass, but after enable it, the output is not
correct.
Signed-off-by: Jason Chen <b02280@freescale.com>
Random artifacts were caused by corruption of the EPDC working
buffer. This occurred because the working buffer was being
allocated too small. This meant other accesses to FB-maintained
buffers was corrupting the working buffer and causing random
data to be drawn to the display. Fixing the working buffer size
causes the artifacts to disappear.
Signed-off-by: Danny Nold <dannynold@freescale.com>
The CS42888 can only playback or record the multiple 44k streams,
as there is only the 22.579MHz Osc on the board. Enable the
ALSA plugin or ASRC when try to playback or record multiple 48k
streams.
Signed-off-by: William Lai <b04597@freescale.com>
Add "w1" setup at mx50 pin defination because 1wire pin used
for usb over current default.
Fix multi w1_setup problem at many i.MX platform. Only first one
is run by main.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
1. At reset_irq, the status of port reset is unsure, maybe the reset
process(hardware does it) is finished, and the status of port reset
is also cleared by usb controller. So it only needs to compare to USBSTS
at usb irq process.
2. Due to mx35/mx25 phy's bug, it needs to reset phy when re-open
usb clock next time(Begin to use usb next time)
3. mdelay 100 seconds is too long for resume process, as this code
is only added for mx37, add arch macro for this mdelay. This can
minimize the effect for other platforms.
4. Compile is ok for all imx platform, functional tests are finished
for mx35 and mx23.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
The clock prescaler can not be 0 for esdhc v3 in MX50.
(The smallest value should be 1).
Change the clock setting part to cover this special case.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
1) Support ELCDIF framebuffer driver.
2) Change CLAA WVGA LCD driver to make it co-work with ELCDIF driver.
Signed-off-by: Liu Ying <b17645@freescale.com>
Set pixel clock rate for CLAA-WVGA LCD panel for 27MHz and
set the display frequency to be 57Hz. This makes the panel
to get rid of water wave glitch issue on MX50 platform.
Signed-off-by: Liu Ying <b17645@freescale.com>
1. adjust lp_clk, ddr_clk MX53 and MX51 uses different one
2. adjust cpu rate in cpu_wp_table
3. enable clock divider handshaking when ddr clock changing
4. add AHB_MED_SET_POINT to ldb_di_clk
5. adjust the bit define about CCDR register
Signed-off-by: Shen Yong <b00984@freescale.com>
1. Adjust VDDGP for 1GHZ as 1.15v
2. Adjust VDDGP for 800MHZ as 1.05v
3. Not all current MX53 boards can run up to 1GHZ. So one limitation is
added into clock.c to limit 1GHZ working point. To enable 1GHZ
working point in kernel, please increase the GP voltage and type the
command "clk core 1000" in uboot console to switch CPU core to 1GHZ.
This limitation will be removed after all boards support 1GHZ.
Signed-off-by: Lily Zhang <r58066@freescale.com>
EPDC driver updated to fail gracefully when the display pmic cannot
be acquired. No longer hanging.
Signed-off-by: Danny Nold <dannynold@freescale.com>
The initial VCOM voltage should be configured once. Previously it was
left unconfigured. Now, the VCOM value is checked the first time
through, and if it is not set correctly, it will be fixed.
Signed-off-by: Danny Nold <dannynold@freescale.com>
A number of Maxim 17135 parts were found to require longer than the
computed max wait time to assert the PWR_GOOD signal, indicating that
display power is up and valid. This fix increases the timeout,
preventing regulator_enable calls from prematurely bailing out
and reporting errors.
Signed-off-by: Danny Nold <dannynold@freescale.com>
MX50 requires inclusion of PxP, Maxim 17135, and EPDC drivers as defaults
in order to have proper E-Ink display support.
Signed-off-by: Danny Nold <dannynold@freescale.com>
