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target/mips: Do not initialize variable used by CPU_FOREACH macro

Browse Source 
The CPU_FOREACH() macro, defined in "hw/core/cpu.h",
ends up calling QTAILQ_FOREACH_RCU() which always
assigns its iterator variable when entering the loop.
Remove the pointless and possibly misleading assignment.

Mechanical patch using the following coccinelle spatch:

  @@
  type T;
  identifier e;
  iterator FOREACH_MACRO =~ ".*_FOREACH.*";
  statement S;
  @@
  -    T *e = ...;
  +    T *e;
       ... when != e
       FOREACH_MACRO(e, ...) S

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2026-05-06 14:42:54 +02:00
parent 734bd83030
commit 4ed05237df
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/misc/mips_cpc.c
View File

@@ -45,7 +45,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
{
CPUState *cs = first_cpu;
CPUState *cs;
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
@@ -63,7 +63,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
{
CPUState *cs = first_cpu;
CPUState *cs;
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;

2
target/mips/internal.h
View File

@@ -280,7 +280,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
static inline int mips_vp_active(CPUMIPSState *env)
{
CPUState *cs = first_cpu;
CPUState *cs;
/* Check if the VP disabled other VPs (which means the VP is enabled) */
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {

8
target/mips/tcg/system/cp0_helper.c
View File

@@ -1570,7 +1570,7 @@ target_ulong helper_dvpe(CPUMIPSState *env)
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPUState *cs = first_cpu;
CPUState *cs;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1590,7 +1590,7 @@ target_ulong helper_evpe(CPUMIPSState *env)
target_ulong prev = cpu->mvp->CP0_MVPControl;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
CPUState *cs = first_cpu;
CPUState *cs;
CPU_FOREACH(cs) {
MIPSCPU *other_cpu = MIPS_CPU(cs);
@@ -1613,7 +1613,7 @@ target_ulong helper_dvp(CPUMIPSState *env)
target_ulong prev = env->CP0_VPControl;
if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
CPUState *cpu = first_cpu;
CPUState *cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);
@@ -1632,7 +1632,7 @@ target_ulong helper_evp(CPUMIPSState *env)
target_ulong prev = env->CP0_VPControl;
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
CPUState *cpu = first_cpu;
CPUState *cpu;
CPU_FOREACH(cpu) {
MIPSCPU *other_cpu = MIPS_CPU(cpu);

2
target/mips/tcg/system/tlb_helper.c
View File

@@ -346,7 +346,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
uint8_t invMsgR = 0;
uint32_t invMsgMMid = env->CP0_MemoryMapID;
CPUState *cpu = first_cpu;
CPUState *cpu;
#ifdef TARGET_MIPS64
invMsgR = extract64(arg, 62, 2);