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configs/target: Implement per-binary TargetInfo structure for riscv

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Defines TargetInfo for 32- and 64-bit riscv binaries.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-6-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Anton Johansson
2025-04-30 14:17:46 +02:00
committed by Philippe Mathieu-Daudé
parent 599a673547
commit 750d25fc66
3 changed files with 53 additions and 0 deletions
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1
configs/targets/meson.build
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@@ -1,5 +1,6 @@
foreach target : [
'arm-softmmu', 'aarch64-softmmu',
'riscv32-softmmu', 'riscv64-softmmu'
]
config_target_info += {target : files(target + '.c')}
endforeach

26
configs/targets/riscv32-softmmu.c Normal file
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@@ -0,0 +1,26 @@
/*
* QEMU binary/target API (qemu-system-riscv32)
*
* Copyright (c) rev.ng Labs Srl.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
static const TargetInfo target_info_riscv32_system = {
.target_name = "riscv32",
.target_arch = SYS_EMU_TARGET_RISCV32,
.long_bits = 32,
.cpu_type = TYPE_RISCV_CPU,
.machine_typename = TYPE_TARGET_RISCV32_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
};
target_info_init(target_info_riscv32_system)

26
configs/targets/riscv64-softmmu.c Normal file
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@@ -0,0 +1,26 @@
/*
* QEMU binary/target API (qemu-system-riscv64)
*
* Copyright (c) rev.ng Labs Srl.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
static const TargetInfo target_info_riscv64_system = {
.target_name = "riscv64",
.target_arch = SYS_EMU_TARGET_RISCV64,
.long_bits = 64,
.cpu_type = TYPE_RISCV_CPU,
.machine_typename = TYPE_TARGET_RISCV64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
};
target_info_init(target_info_riscv64_system)