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hw/arm/aspeed: Consolidate secure SRAM into SRAM array

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Some Aspeed SoCs contain multiple SRAM regions with different
sizes and MMIO mappings, such as internal SRAM and secure SRAM.

The current implementation models secure SRAM separately from the
generic SRAM representation, which complicates future multi-SRAM
support and expansion.

Increase ASPEED_SRAM_NUM to 2 and migrate secure SRAM to use the
common SRAM array representation. Rename the secure SRAM memmap
entry to ASPEED_DEV_SRAM1 and update AST10x0 to initialize both
SRAM regions through sram[] and sram_size[].

This unifies SRAM-like regions under a common representation and
prepares for future SoCs with additional SRAM regions.

No functional change.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin
2026-05-25 05:30:43 +00:00
committed by Cédric Le Goater
parent 598a9ecf25
commit 8c6cf9ef47
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
hw/arm/aspeed_ast10x0.c
View File

@@ -21,7 +21,7 @@
static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SRAM0] = 0x00000000,
[ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_SRAM1] = 0x79000000, /* SEC SRAM */
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
[ASPEED_DEV_FMC] = 0x7E620000,
@@ -249,14 +249,16 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
/* Internal SEC SRAM */
memory_region_init_ram(&s->sram[1], OBJECT(s), "sec.sram",
sc->sram_size[1], &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
}
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
&s->secsram);
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
&s->sram[1]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -494,7 +496,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
sc->wdts_num = 4;
@@ -522,7 +524,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1060_A2_SILICON_REV;
sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->wdts_num = 4;
sc->uarts_num = 1;

6
include/hw/arm/aspeed_soc.h
View File

@@ -60,7 +60,7 @@
#define ASPEED_PCIE_NUM 3
#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
#define ASPEED_SRAM_NUM 1
#define ASPEED_SRAM_NUM 2
struct AspeedSoCState {
DeviceState parent;
@@ -89,7 +89,6 @@ struct AspeedSoCState {
AspeedSBCState sbc;
AspeedSLIState sli;
AspeedSLIState sliio;
MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
AspeedPWMState pwm;
@@ -173,7 +172,6 @@ struct AspeedSoCClass {
const char * const *valid_cpu_types;
uint32_t silicon_rev;
uint64_t sram_size[ASPEED_SRAM_NUM];
uint64_t secsram_size;
int pcie_num;
int spis_num;
int sgpio_num;
@@ -225,10 +223,10 @@ enum {
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_SBC,
ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM0,
ASPEED_DEV_SRAM1,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,