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Author SHA1 Message Date
Stefan Hajnoczi
c3a63b7c06 Merge tag 'hw-misc-20260707' of https://github.com/philmd/qemu into staging 
Misc HW patches

- MAINTAINERS update
- Fix in few trace event formats
- A pair of improvements in util/
- FlexCAN3 to imx8mp-evk board
- Various fixes in hw/
  (EDU, ATI VGA, IDE AHCI, PCA9552, i8257 DMA,
   e1000e/igb, MPT SAS, Hyper-V, QXL, M25P80)

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# gpg: Signature made Tue 07 Jul 2026 17:12:08 CEST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20260707' of https://github.com/philmd/qemu: (36 commits)
  MAINTAINERS: update Chao Liu's email address
  Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles"
  Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command"
  hw/ssi: aspeed_smc: Fix direct-read dummy bytes
  hw/ssi: xilinx_spips: Fix dummy phase handling
  hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic
  hw/block: m25p80: Fix dummy byte handling for Spansion flash
  hw/arm/msf2-som: Fix spansion-cr2nv value for S25FL128S
  hw/block: m25p80: Fix dummy byte handling for Macronix flash
  hw/block: m25p80: Fix dummy byte handling for Numonyx/Micron flash
  hw/block: m25p80: Fix dummy byte handling for Winbond flash
  backends/iommufd: Fix dev_id and type order in viommu trace
  hw/acpi/ich9: move initial property values into ich9_reset_properties()
  hw/rtc/mc146818rtc: convert date from object prop to class prop
  hw/arm: Add basic FlexCAN3 support to TYPE_FSL_IMX8MP and imx8mp-evk
  hw/arm/imx8mp-evk: Introduce FslImx8mpEvkState
  hw/arm/imx8mp-evk: Open code DEFINE_MACHINE_AARCH64
  hw/net/can/flexcan: Subclass TYPE_CAN_FLEXCAN
  hw/net/can/flexcan: Wire clock control module via link property
  hw/intc/loongarch_dintc: Fix OOB access in DINT MMIO write handler
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-07 19:19:33 +02:00
Bernhard Beschow
7a4775d07f hw/arm: Add basic FlexCAN3 support to TYPE_FSL_IMX8MP and imx8mp-evk 
Real hardware supports CAN FD which is missing in the emulation and is
considered future work. Still, CAN communication already works under Linux.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Acked-by: Pavel Pisa <pisa@fel.cvut.cz>
Tested-by: Pavel Pisa <pisa@fel.cvut.cz>
Message-ID: <20260702184038.178196-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
 2026-07-07 17:10:24 +02:00
Daniel P. Berrangé
58b70f21ba docs: mark '-mon' as deprecated in favour of -object 
The high level `-qmp` and `-monitor` options can remain as convenience
wrappers, but the low level `-mon` is completed obsoleted by the new
`-object` support with 'monitor-qmp' and 'monitor-hmp' types.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Tested-by: Peter Krempa <pkrempa@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20260706135824.2623960-36-berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Editing accident fixed in qemu-options.hx]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
 2026-07-07 11:16:27 +02:00
Stefan Hajnoczi
94826ec137 Merge tag 'accel-20260706' of https://github.com/philmd/qemu into staging 
Accelerators patches queue

- Various cleanups around debugging APIs
- Correctly check singlestep flag enabled in CPUState
- Fix possible memory corruption with MSHV (CID 1660876)

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# gpg: Signature made Mon 06 Jul 2026 15:43:56 CEST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'accel-20260706' of https://github.com/philmd/qemu: (32 commits)
  cpu: Only check SSTEP_ENABLE flag in cpu_single_stepping()
  cpu: Rename CPUState @singlestep_enabled -> @singlestep_flags
  cpu: Introduce cpu_single_stepping() helper
  cpu: Better name cpu_single_step() trace event
  accel/tcg: Improve docstrings around TCGCPUOps::*watchpoint* handlers
  target/ppc: Ensure TCG is used in ppc_update_daw()
  target/arm: Inline check_watchpoints() in arm_debug_check_watchpoint()
  accel: Use GdbBreakpointType enum
  gdbstub: Introduce GdbBreakpointType enumerator
  gdbstub: Reduce @type variable scope
  gdbstub/user: Directly call gdb_breakpoint_remove_all() in user mode
  accel: Remove unnecessary 'inline' qualifier in remove_all_breakpoints
  cpu: Move BREAKPOINT definitions to 'exec/breakpoint.h'
  cpu: Move cpu_breakpoint_test out of line
  accel: Remove AccelOpsClass::supports_guest_debug
  accel: Hold @can_reverse information in AccelGdbConfig
  gdbstub: Make default replay_mode value explicit in stubs
  accel: Have each implementation return their AccelGdbConfig
  gdbstub: Move supported_sstep_flags in AccelGdbConfig structure
  gdbstub: Reduce gdb_supports_guest_debug() scope
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:38:14 +02:00
Stefan Hajnoczi
d0edff8ee1 Merge tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu into staging 
target-arm queue:
 * hw/net/fsl_etsec: validate FCB offsets in process_tx_fcb()
 * hw/arm/smmuv3-accel: Fix veventq read returning true on EAGAIN/EINTR
 * target/arm: Only evaluate SCR_EL3.PIEN if ARM_FEATURE_EL3 is present
 * hw/arm: use cortex-a9 mpcore base for CBAR on npcm7xx machines
 * docs/specs/fw_cfg: Document all architecture register layouts
 * hw/nvram/fw_cfg: Simplify functions so board models don't have
   the opportunity to create non-standard fw_cfg register layouts
 * hw/misc: use tracepoints rather than DPRINTF in imx ccm models
 * hw/arm: add support for shim loading
 * docs/system/arm: Document Zynq Buildroot boot
 * target/arm: Report correct syndrome to AArch32 EL2 for trapped
   Neon/VFP insns
 * target/arm: implement WFET to not be a NOP
 * target/arm: Emulate FEAT_SME_MOP4
 * target/arm: Emulate FEAT_FPRCVT
 * target/arm: Emulate FEAT_SSVE_FEXPA

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# gpg: Signature made Mon 06 Jul 2026 12:36:41 CEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu: (49 commits)
  target/arm: Define fields for NSACR
  target/arm: Report correct syndrome to AArch32 EL2 for trapped Neon/VFP insns
  target/arm: Separate syndrome functions for A32 and A64
  target/arm: Separate out Neon from VFP access checks
  target/arm: Enable FEAT_SME_MOP4 for -cpu max
  target/arm: Implement USMOP4[AS]
  target/arm: Implement UMOP4[AS] (4-way)
  target/arm: Implement UMOP4[AS] (2-way)
  target/arm: Implement SUMOP4[AS]
  target/arm: Implement SMOP4[AS] (4-way)
  target/arm: Implement SMOP4[AS] (2-way)
  target/arm: Implement FMOP4A (widening, 2-way, FP8 to FP16)
  target/arm: Implement FMOP4 (widening, 4-way fp8 to fp32)
  target/arm: Implement FMOP4 (widening, 2-way fp16 to fp32)
  target/arm: Implement BFMOP4 (widening)
  target/arm: Implement BFMOP4 (non-widening)
  target/arm: Implement FMOP4 (non-widening) for float64
  target/arm: Implement FMOP4 (non-widening) for float16
  target/arm: Implement FMOP4 (non-widening) for float32
  docs/system/arm: Document Zynq Buildroot boot
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:37:28 +02:00
Stefan Hajnoczi
48560f0d96 Merge tag 'pull-ppc-for-11.1-sf-20260706' of https://gitlab.com/harshpb/qemu into staging 
PPC PR for 11.1 Soft-freeze

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# gpg: Signature made Mon 06 Jul 2026 10:20:12 CEST
# gpg:                using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [full]
# gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [full]
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-11.1-sf-20260706' of https://gitlab.com/harshpb/qemu:
  MAINTAINERS: Add self as maintainer for PowerNV
  ppc/pnv: Remove Power8E and Power8NVL CPUs
  ppc/pnv: Remove Power8E and Power8NVL pnv chips
  ppc/pnv: Replace Power8E with Power11 for 'none' machine test
  tests/functional: Use default powernv machine instead of power10
  tests/qtest: Add Power11 chip & machine to qtests
  tests/qtest/pnv_spi: Test Power11 PNV_SPI
  tests/functional: Add remote interrupts test for PowerNV

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:36:52 +02:00
Stefan Hajnoczi
9a84bbf230 Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging 
pci, vhost, virtio, iommu: features, fixes, cleanups

A new sp-mem device
New tests for vtd
New seg-max-adjust flag for vhost-user-blk
Watchdog support for arm/virt

Fixes, cleanups all over the place.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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# gpg: Signature made Sun 05 Jul 2026 15:19:16 CEST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (44 commits)
  virtio-net: validate RSS indirections_len in post_load
  vhost-user-blk: add seg-max-adjust flag
  vhost-user-scmi: free vhost virtqueue array on cleanup
  hw/virtio-crypto: enforce max akcipher key length
  vhost-user: Guarantee that memory regions do not overlap
  tests: acpi: arm/virt: update expected GTDT blob
  tests: acpi: arm/virt: add GTDT watchdog table test case
  tests: acpi: arm/virt: whitelist GTDT table
  tests: acpi: arm/virt: update expected WDAT blob
  tests: acpi: arm/virt: add WDAT table test case
  tests: acpi: arm/virt: whitelist new WDAT table
  arm: virt: add support for WDAT based watchdog
  acpi: introduce WDAT table for GWDT
  arm: sbsa-gwdt: add 'wdat' option
  arm: virt: create sbsa-gwdt watchdog
  arm: sbsa_gwdt: rename device type to sbsa-gwdt
  arm: add tracing events to sbsa_gwdt
  arm: sbsa_gwdt: fixup default "clock-frequency"
  vdpa: fix use-after-free of vqs in vhost_vdpa_device_unrealize
  vhost-user-base: clean up vhost_dev on realize failure
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-06 18:33:19 +02:00
Philippe Mathieu-Daudé
0533f08413 accel: Remove AccelOpsClass::supports_guest_debug 
Now accelerators hold the 'guest debug supported' information
in their state, accessible by the common code. No need to call
a per-accelerator handler, simply check for the SSTEP_ENABLE
in AccelGdbConfig::sstep_flags.

Remove all AccelOpsClass::supports_guest_debug implementations,
inline gdb_supports_guest_debug() and remove the now unnecessary
KVMState::have_guest_debug field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260705215729.62196-18-philmd@oss.qualcomm.com>
 2026-07-06 15:42:18 +02:00
Richard Henderson
82d7e57204 target/arm: Enable FEAT_SME_MOP4 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260702204314.79224-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Bin Meng
2224a77f41 docs/system/arm: Document Zynq Buildroot boot 
The Zynq board documentation only showed a generic direct kernel
boot command.

Add Buildroot ZC702 commands for booting through U-Boot proper
with the generic loader and for direct Linux boot from the
generated SD image.

Signed-off-by: Bin Meng <bin.meng@processmission.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20260628114925.418293-1-bin.meng@processmission.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Richard Henderson
272eef0d25 target/arm: Implement and enable FEAT_SSVE_FEXPA for -cpu max 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260626164819.770787-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Jim MacArthur
81555a662b docs/system/arm: Add FEAT_FPRCVT to A-profile support 
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
Message-id: 20260630-jmac-fprcvt-v3-5-f4840d5e0a7f@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-07-06 11:32:01 +01:00
Aditya Gupta
f73b31686f ppc/pnv: Remove Power8E and Power8NVL CPUs 
Power8E and Power8NVL were deprecated since QEMU 10.1, with
commit 264a604e71 ("target/ppc: Deprecate Power8E and Power8NVL")

Remove the corresponding 8E and 8NVL CPU cores from spapr/pseries

Also, with no use of 8E and 8NVL, in powernv chips or spapr cores,
remove the CPU definitions for the cores

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Tested-by: Misbah Anjum N <misanjum@linux.ibm.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260703085955.2318600-8-adityag@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
 2026-07-06 12:06:47 +05:30
Aditya Gupta
cfa89bd78a ppc/pnv: Remove Power8E and Power8NVL pnv chips 
Power8E and Power8NVL were deprecated since QEMU 10.1, with
commit 264a604e71 ("target/ppc: Deprecate Power8E and Power8NVL")

Accordingly, remove usage of 8E and 8NVL chips from powernv, as it's old
and unmaintained now.

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Tested-by: Misbah Anjum N <misanjum@linux.ibm.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260703085955.2318600-7-adityag@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
 2026-07-06 12:06:47 +05:30
Igor Mammedov
285bc90d5b arm: virt: add support for WDAT based watchdog 
Add WDAT handling for sbsa-gwdt on arm/virt machine.

WDAT mode is enabled by 'wdat' option: ex: "-device sbsa-gwdt,wdat=on"

When WDAT is enabled:
 - Build the WDAT ACPI table instead of the GTDT watchdog entry,
   since they are mutually exclusive due to different timer
   resolution (WDAT uses 1 kHz vs GTDT's system counter frequency).
 - Skip FDT watchdog node creation, as the DT-based Linux driver
   would use the system counter frequency which doesn't match the
   WDAT-mode 1 kHz clock.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20260702145856.1539572-8-imammedo@redhat.com>
 2026-07-05 09:06:13 -04:00
Igor Mammedov
2f27572eb5 arm: virt: create sbsa-gwdt watchdog 
Allow to use SBSA generic watchdog with virt machine type.
(includes conditional generation of corresponding FDT and
ACPI GTDT descriptors)

Use '-device sbsa-gwdt' to command line to enable it.

Instead of using dynamic sysbus infra to wire up MMIO/IRQ/FDT,
statically assign resources in machine's mem/irq maps and wire
them up at device (pre_)plug handlers. It's similar to dynamic
sysbus wiring, modulo resources are nailed down statically,
and wiring is limited to virt machine only.
(Benefit is that tests don't break anymore on rebase due to
address being stable)

Tested with Fedora 43:
  FDT: -M virt,acpi=off -device sbsa-gwdt
  ACPI: -M virt -device sbsa-gwdt

Note:
Windows sees GTDT, initializes watchdog but instead pinging WRR
it sets/advances WOR to way too large value, so it's never going
to trigger watchdog reboot (it's Windows driver issue though).

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20260702145856.1539572-5-imammedo@redhat.com>
 2026-07-05 09:06:13 -04:00
Thomas Huth
75f3c97476 docs/system/ppc/pseries: Update the link to the SLOF repository 
SLOF has been moved to gitlab.com already a while ago. We updated
the link in pc-bios/README in commit 7f98b4f25e ("pseries: Update
SLOF firmware image"), but forgot to update it in the manual, too.

Signed-off-by: Thomas Huth <th.huth@posteo.eu>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260702074842.4806-1-th.huth@posteo.eu
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
 2026-07-03 10:07:21 +05:30
Stefan Hajnoczi
a59157f98f Merge tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu into staging 
RISC-V PR for 11.1

* Fix IMSIC CSR write and add tests
* Parametrise debug trigger number
* Add 'svbare' satp-mode
* Fix RINTC PLIC context ID for KVM
* Avoid abort when reading vtype before env->xl is set
* Skip reset for KVM irqchip
* Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE
* More FDT cleanups (PLIC)
* Make FCTL.BE in IOMMU read only 0
* Check DC.TC reserved bits in IOMMU
* Apply UXL WARL handling to vsstatus
* Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU
* Set RISCV_IOMMU_FQ_HDR_PV appropriately
* Fix MSI MRIF IOMMU interrupt-pending offset
* Report QEMU CPU archid as 42
* Check PMP before updating PTE
* Add the Tenstorrent Atlantis machine

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* tag 'pull-riscv-to-apply-20260701' of https://github.com/alistair23/qemu: (39 commits)
  hw/riscv/riscv-iommu.c: always fault with SADE=0 and A=0
  hw/riscv/atlantis: Add some i2c peripherals
  hw/riscv/atlantis: Integrate i2c controllers
  hw/i2c: Add DesignWare I2C Controller
  tests/functional/riscv64: Add tt-atlantis tests
  hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr
  hw/riscv: Add Tenstorrent Atlantis machine
  target/riscv: tt-ascalon: Enable Zkr extension
  hw/riscv/aia: Configure stride for the M-mode IMSIC
  hw/riscv/aia: Provide number of irq sources
  hw/riscv/virt: Move AIA initialisation to helper file
  hw/riscv/boot: Account for discontiguous memory when loading firmware
  hw/riscv/boot: Describe discontiguous memory in boot_info
  target/riscv: Check PMP before updating PTE
  target/riscv: Report QEMU CPU archid as 42
  hw/riscv/riscv-iommu.c: fix MSI MRIF interrupt-pending offset
  hw/riscv/riscv-iommu.c: set RISCV_IOMMU_FQ_HDR_PV appropriately
  hw/riscv/riscv-iommu: set cmd_ill IOFENCE.C rsvp bits are set
  target/riscv: Apply UXL WARL handling to vsstatus
  hw/riscv/riscv-iommu: check DC.TC reserved bits
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-02 10:44:50 +02:00
Stefan Hajnoczi
654b54fb37 Merge tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu into staging 
target-arm queue:
 * hw/timer/imx_epit: Replace DPRINTF with trace events
target/arm: Enable SCTLR_EL1.EnFPM for user-only
target/arm: Implement FEAT_SME_F8F32
target/arm: Implement FEAT_SSVE_AES
target/arm: Implement FEAT_SME_F8F16
target/arm: GICv5: Fix some minor bugs
target/arm: Add GPC3 granule bypass windows
target/arm: Fix some minor timer related bugs
hw/arm/sabrelite: Add FlexCAN emulation
docs/system: add FEAT_ECV_POFF to the emulation list
docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV

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# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260629' of https://gitlab.com/pm215/qemu: (54 commits)
  docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV
  target/arm: Enable FEAT_SME_F8F16 for -cpu max
  target/arm: Implement FVDOT (FP8 to FP16)
  target/arm: Rename FVDOT pattern
  target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16)
  target/arm: Implement FDOT (multiple and indexed, FP8 to FP16)
  target/arm: Implement FDOT (multiple, multiple and single, FP8 to FP16)
  target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16)
  target/arm: Implement FMLAL (multiple, multiple and single, FP8 to FP16)
  target/arm: Rename SME FMLAL/FMLSL patterns
  target/arm: Enable FADD/FSUB (half-precision) with FEAT_SME_F8F16
  docs/system: add FEAT_ECV_POFF to the emulation list
  target/arm: trigger timer recalc on HCR:(E2H|TGE) changes
  target/arm: gate check on scr_el3 behind ARM_FEATURE_EL3 check
  target/arm: trigger timer recalc on SCR:ECVEN change
  target/arm: trigger timer recalculation when toggling CNTHCTL:ECV
  target/arm: split evaluation of CNTHCTL timer IRQ masks
  docs/arm/sabrelite: Mention FlexCAN support
  tests: Add qtests for FlexCAN
  hw/arm: Plug FlexCAN into FSL_IMX6 and Sabrelite
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-07-02 10:44:27 +02:00
Joel Stanley
7778f4b27b hw/riscv: Add Tenstorrent Atlantis machine 
The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
and CoreLab Technology. It is based on the Atlantis SoC, which includes
the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
RISC-V CPU.

Add the tt-atlantis machine containing serial console, interrupt
controllers, and device tree support.

The Atlantis boot images loaded from include OpenSBI and an initial DTB
that is passed to OpenSBI. This is approximated in the model by having
QEMU build the device tree rather than load a DTB image directly.
Subsequent stages may use the modified DTB provided by OpenSBI or opt to
supply their own.

  qemu-system-riscv64 -M tt-atlantis -m 512M \
   -kernel Image -initrd rootfs.cpio -nographic

Co-Developed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260630024952.1520546-8-joel@jms.id.au>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2026-07-01 19:59:10 +10:00
Brian Cain
234133b916 docs/system: Add hexagon CPU emulation 
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
 2026-06-29 06:02:59 -07:00
Brian Cain
066bc54e06 docs: Add hexagon sysemu docs 
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
 2026-06-29 06:02:59 -07:00
Shameer Kolothum
94e3ad7800 docs/system/arm/virt: Document accelerated SMMUv3 and Tegra241 CMDQV 
Add subsections for accel=on (nested Stage-1/Stage-2 translation) and
cmdqv (Tegra241 CMDQV hardware command queues) under "User-creatable
SMMUv3 devices".

Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
Message-id: 20260623104003.36590-1-skolothumtho@nvidia.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:06:02 +01:00
Richard Henderson
c3da6e9f75 target/arm: Enable FEAT_SME_F8F16 for -cpu max 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260625015159.719300-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:03:47 +01:00
Alex Bennée
08d5f3960b docs/system: add FEAT_ECV_POFF to the emulation list 
We already had this implemented since 2808d3b38a (target/arm:
Implement FEAT_ECV CNTPOFF_EL2 handling) but it has its own feature
name now. Add it to the list.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20260624124527.1018912-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:03:47 +01:00
Matyáš Bobek
e2929b3bc9 docs/arm/sabrelite: Mention FlexCAN support 
Also added example command line usage of the Sabrelite board
with FlexCAN controllers.

Signed-off-by: Matyáš Bobek <matyas.bobek@gmail.com>
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
Tested-by: Pavel Pisa <pisa@fel.cvut.cz>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Pavel Pisa <pisa@fel.cvut.cz>
Message-id: 19407fc30bdf6b264d1c093a82903609e9cfee48.1782140438.git.matyas.bobek@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:03:47 +01:00
Richard Henderson
69f3323ef5 target/arm: Enable FEAT_SME_F8F32 for -cpu max 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260618041517.573469-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:03:46 +01:00
Richard Henderson
4bdbb20240 target/arm: Implement FEAT_SSVE_AES 
Enable FEAT_SVE_AES instructions in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260618040718.572950-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-29 11:03:46 +01:00
Linisha
ee03a20aab docs/system: add general note about architecture and machine differences 
Add a note near the start of the introduction explaining that QEMU
options, properties, and command lines may differ between target
architectures and machine types. This helps prevent confusion when
examples shown for one architecture do not work for another, such as
the pflash0/pflash1 options visible in -machine help on some machines
but not others.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/3254
Signed-off-by: Linisha <linisha232@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260626181118.1136-1-linisha232@gmail.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
 2026-06-26 12:10:41 -07:00
Gerd Hoffmann
717cd7bc76 add a note on -shim to direct kernel boot docs 
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260612161707.158029-1-kraxel@redhat.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
 2026-06-16 10:54:58 -07:00
Chao Liu
b3fe55196f docs/system/riscv: add documentation for k230 machine 
Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <81d2e2fa42ecabf638f841321cf36cee8f10af01.1781246408.git.chao.liu@processmission.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2026-06-16 20:01:11 +10:00
Djordje Todorovic
a8dc227c83 target/riscv: Expose and document the CPU 'big-endian' property 
Now that the full big-endian data path is in place (runtime MSTATUS
bits, boot code, and page-table walks), expose the "big-endian"
property to users via DEFINE_PROP_BOOL and document it in
docs/system/target-riscv.rst.

Document that the property models fixed-endian hardware: it selects
harts whose MBE/SBE/UBE fields are fixed to 1, and it does not model
a mixed-endian implementation where software can toggle those bits at
runtime.

The property can be enabled from the command line, e.g.:

    -cpu <cpu>,big-endian=on

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20260527201348.29511-12-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 2026-06-16 13:53:36 +10:00
Richard Henderson
c45b02cb24 target/arm: Enable FEAT_F8F16MM for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
97f97d15c7 target/arm: Enable FEAT_F8F32MM for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
c67d5463da target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
908c7a23d5 target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
07e9ea8f1c target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
332ec0f79b target/arm: Enable FEAT_SME_LUTv2 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
a918a18f0e target/arm: Enable FEAT_FP8 for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Richard Henderson
215ad1fa32 target/arm: Enable FEAT_LUT for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:40 +01:00
Gabriel Brookman
f35b6418cc docs: add MTE4 features to docs 
The implemented MTE4 features are now present in
docs/system/arm/emulation.rst

Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260529-feat-mte4-v7-13-ccbd3c14eb3c@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-06-10 16:54:25 +01:00
Jason Wright
7e637052fa target/arm: advertise FEAT_RNG_TRAP on cortex-max 
Set ID_AA64PFR1.RNDR_TRAP=1 on the max CPU model so guests and
firmware detect FEAT_RNG_TRAP, per the Arm Architecture Reference
Manual for A-profile architecture (DDI 0487), and document the feature
as emulated in docs/system/arm/emulation.rst.

Signed-off-by: Jason Wright <wrigjl@proton.me>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-29 09:44:03 +01:00
Richard Henderson
5e18eaab88 target/arm: Enable FEAT_CMPBR for -cpu max 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260518174750.660258-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-28 15:06:23 +01:00
Stefan Hajnoczi
3f89b5de5b Merge tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu into staging 
target-arm queue:
 * hw/timer/mss_timer: Remove dead code in timer_write()
 * OMAP: Remove various pieces of dead code
 * target/arm: Set debug in attrs in translate_for_debug()
 * target/arm/ptw: Flip sense of get_phys_addr_* return values
 * tests/functional/aarch64: Bump up timeout on vbsa
 * target/arm: Fix minor FEAT_AFP corner case bugs
 * target/arm: Implement FEAT_FAMINMAX
 * target/arm: Implement FEAT_FPMR
 * target/arm: Some initial patches towards other FP8 features

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# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu: (54 commits)
  target/arm: Move vectors_overlap to vec_internal.h
  target/arm: Split vector-type.h from cpu.h
  target/arm: Implement FSCALE for SME
  target/arm: Implement FSCALE for AdvSIMD
  target/arm: Add isar_feature_aa64_f8cvt
  target/arm: Implement ID_AA64FPFR0
  target/arm: Enable FEAT_FPMR for -cpu max
  linux-user/aarch64: Implement FPMR signal frames
  target/arm: Dump FPMR when present
  tests/functional/aarch64/rme: update images to support FEAT_FP8
  target/arm: Trap direct acceses to FPMR
  target/arm: Add FPMR_EL to TBFLAGS
  target/arm: Clear FPMR on ResetSVEState
  target/arm: Enable EnFPM bits for FEAT_FPMR
  target/arm: Update SCTLR bits for FEAT_FPMR
  target/arm: Introduce FPMR
  target/arm: Update HCRX bits for Arm ARM M.a.a
  target/arm: Update SCR bits for Arm ARM M.a.a
  target/arm: Enable FEAT_FAMINMAX for -cpu max
  target/arm: Implement FEAT_FAMINMAX for SVE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 13:20:15 -04:00
Richard Henderson
2430d49a17 target/arm: Enable FEAT_FPMR for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
697910f67f target/arm: Enable FEAT_FAMINMAX for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Jamin Lin
4ed26771eb docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board 
Update the Aspeed AST10x0 documentation to include the
AST1040 evaluation board and clarify the AST10x0 family
classification.

The documentation now describes:
- AST1030 and AST1040 as Bridge IC devices
- AST1060 as a Platform Root of Trust processor
- AST1040 Cortex-M4F CPU frequency running at 400 MHz

Also add the ast1040-evb machine entry to the supported
AST10x0 SoC based machine list.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
 2026-05-26 07:13:49 +02:00
William de Abreu Pinho
dc238e34f2 hw/arm/aspeed: add anacapa-bmc machine 
Add the Facebook Anacapa BMC machine.  The I2C topology is based on the
Linux kernel device tree [1].  Hardware strap register values are taken
from real hardware.

A functional test is included using the OpenBMC image built from [2],
similar to the tests for bletchley-bmc and catalina-bmc.

[1]: 76b4ec8efd/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
[2]: 8e22df918e

Signed-off-by: William de Abreu Pinho <williamdapinho@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260519-add-anacapa-machine-v3-2-56c23993a20a@gmail.com
[ clg: docs/system/arm/aspeed.rst : fixed 'Aspeed family boards' title change ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
 2026-05-24 23:14:14 +02:00
Philippe Mathieu-Daudé
630decdfcc buildsys: Remove MIPS KVM 
We removed support for MIPS host. The KVM MIPS code
is now unreachable, remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260511135312.38705-5-philmd@linaro.org>
 2026-05-21 08:20:58 +02:00
Thomas Huth
3822df47c2 Remove the deprecated glusterfs block driver 
Glusterfs has been marked as deprecated since QEMU v9.2, and as far
as I know, nobody spoke up 'til today that it should be kept.
The listed e-mail address integration@gluster.org in our MAINTAINERS
file seems to be bouncing nowadays, and looking at their website
https://www.gluster.org/ the most recent news are from 2020 / 2021 ...
so it seems like there is really hardly any interest in Glusterfs
anymore. Thus it's time to remove the code now from QEMU.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260511063013.39805-1-thuth@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
 2026-05-19 17:25:48 +02:00