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Merge tag 'mips-20260707' of https://github.com/philmd/qemu into staging

Browse Source 
MIPS and SuperH patches queue

- MIPS Octeon COP2 crypto opcodes
- Fix for SH4 FIPR/FTRV vector math opcodes

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Jul 2026 20:15:04 CEST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20260707' of https://github.com/philmd/qemu: (23 commits)
  qemu-options: Do not list -enable-kvm on MIPS binaries
  target/sh4: fixup tcg for sh4 fipr/ftrv instructions
  tests/tcg/mips: cover Octeon QMAC instructions
  target/mips: add Octeon CvmCount RDHWR support
  target/mips: decode Octeon CHORD and LLM COP2 selectors
  target/mips: decode Octeon block-cipher COP2 selectors
  target/mips: decode Octeon ZUC and SNOW3G COP2 selectors
  target/mips: decode Octeon HSH and SHA3 COP2 selectors
  target/mips: decode Octeon CRC and GFM COP2 selectors
  target/mips: decode Octeon COP2 register selectors
  target/mips: add Octeon CHORD and LLM COP2 helpers
  target/mips: add Octeon HSH COP2 helpers
  target/mips: add Octeon Camellia COP2 helpers
  target/mips: add Octeon 3DES and KASUMI COP2 helpers
  target/mips: add Octeon SMS4 COP2 helpers
  target/mips: add Octeon AES COP2 helpers
  target/mips: add Octeon SNOW3G COP2 helpers
  target/mips: add Octeon ZUC COP2 helpers
  target/mips: add Octeon SHA3 COP2 helpers
  target/mips: add Octeon GFM COP2 helpers
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2026-07-08 15:59:50 +02:00
parent c3a63b7c06 f086625548
commit 2c8cf1f16d
15 changed files with 3437 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
qemu-options.hx
View File

@@ -5179,7 +5179,7 @@ ERST
DEF("enable-kvm", 0, QEMU_OPTION_enable_kvm, \
"-enable-kvm enable KVM full virtualization support\n",
QEMU_ARCH_ARM | QEMU_ARCH_I386 | QEMU_ARCH_MIPS | QEMU_ARCH_PPC |
QEMU_ARCH_ARM | QEMU_ARCH_I386 | QEMU_ARCH_PPC |
QEMU_ARCH_RISCV | QEMU_ARCH_S390X)
SRST
``-enable-kvm``

68
target/mips/cpu.c
View File

@@ -26,6 +26,7 @@
#include "cpu.h"
#include "internal.h"
#include "qemu/module.h"
#include "qemu/qtree.h"
#include "system/qtest.h"
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev-clock.h"
@@ -181,6 +182,57 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "cpu-defs.c.inc"
static gint mips_octeon_u64_tree_compare(gconstpointer a, gconstpointer b,
gpointer user_data)
{
uint64_t av = *(const uint64_t *)a;
uint64_t bv = *(const uint64_t *)b;
return (av > bv) - (av < bv);
}
QTree *mips_octeon_llm_tree_new(void)
{
return q_tree_new_full(mips_octeon_u64_tree_compare,
NULL, g_free, g_free);
}
uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr)
{
uint64_t key = addr;
uint64_t *value = tree ? q_tree_lookup(tree, &key) : NULL;
return value ? *value : 0;
}
void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value)
{
uint64_t *key;
uint64_t *stored;
if (!*treep) {
*treep = mips_octeon_llm_tree_new();
}
key = g_new(uint64_t, 1);
stored = g_new(uint64_t, 1);
*key = addr;
*stored = value;
q_tree_replace(*treep, key, stored);
}
static void mips_octeon_destroy_llm_state(MIPSOcteonCryptoState *crypto)
{
if (crypto->llm36) {
q_tree_destroy(crypto->llm36);
crypto->llm36 = NULL;
}
if (crypto->llm64) {
q_tree_destroy(crypto->llm64);
crypto->llm64 = NULL;
}
}
static void mips_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
@@ -192,6 +244,7 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
mcc->parent_phases.hold(obj, type);
}
mips_octeon_destroy_llm_state(&env->octeon_crypto);
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
/* Reset registers to their default values */
@@ -246,6 +299,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
if (env->insn_flags & INSN_OCTEON) {
env->octeon_crypto.chord = 1;
}
#if defined(CONFIG_USER_ONLY)
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
@@ -262,6 +318,10 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
* hardware registers.
*/
env->CP0_HWREna |= 0x0000000F;
if (env->insn_flags & INSN_OCTEON) {
env->CP0_HWREna |= 0x40000000u;
env->CP0_HWREna |= 0x80000000u;
}
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
env->CP0_Status |= (1 << CP0St_CU1);
}
@@ -417,6 +477,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
#endif
}
static void mips_cpu_finalize(Object *obj)
{
MIPSCPU *cpu = MIPS_CPU(obj);
mips_octeon_destroy_llm_state(&cpu->env.octeon_crypto);
}
static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)
{
const MIPSCPU *cpu = MIPS_CPU(cs);
@@ -645,6 +712,7 @@ static const TypeInfo mips_cpu_type_info = {
.instance_size = sizeof(MIPSCPU),
.instance_align = __alignof(MIPSCPU),
.instance_init = mips_cpu_initfn,
.instance_finalize = mips_cpu_finalize,
.abstract = true,
.class_size = sizeof(MIPSCPUClass),
.class_init = mips_cpu_class_init,

31
target/mips/cpu.h
View File

@@ -11,6 +11,7 @@
#include "fpu/softfloat-types.h"
#include "hw/core/clock.h"
#include "mips-defs.h"
#include "qemu/qtree.h"
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
@@ -537,6 +538,34 @@ struct TCState {
};
struct MIPSITUState;
typedef struct MIPSOcteonCryptoState {
union {
struct {
uint64_t hsh_dat[16];
uint64_t hsh_iv[8];
uint64_t sha3_dat24;
};
uint64_t sha3_dat[25];
};
uint64_t des3_key[3];
uint64_t des3_iv;
uint64_t des3_result;
uint64_t aes_resinp[2];
uint64_t aes_iv[2];
uint64_t aes_key[4];
uint32_t crc_poly;
uint32_t crc_iv;
uint64_t gfm_mul[2];
uint64_t gfm_resinp[2];
uint16_t gfm_poly;
uint8_t aes_keylen;
uint8_t crc_len;
uint64_t chord;
uint64_t llm_data[2];
QTree *llm36;
QTree *llm64;
} MIPSOcteonCryptoState;
typedef struct CPUArchState {
TCState active_tc;
CPUMIPSFPUContext active_fpu;
@@ -558,6 +587,8 @@ typedef struct CPUArchState {
#define MSAIR_ProcID 8
#define MSAIR_Rev 0
MIPSOcteonCryptoState octeon_crypto;
/*
* CP0 Register 0
*/

61
target/mips/helper.h
View File

@@ -25,6 +25,65 @@ DEF_HELPER_3(crc32, tl, tl, tl, i32)
DEF_HELPER_3(crc32c, tl, tl, tl, i32)
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
/* Octeon COP2 selector operation helpers. */
DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env)
DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env)
DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env)
DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env)
DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env)
DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_polynomial_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_half, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_word, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_byte_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_half_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_word_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect0, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64)
DEF_HELPER_1(octeon_cp2_mt_sha3_startop, void, env)
DEF_HELPER_2(octeon_cp2_mt_zuc_start, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_zuc_more, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_snow3g_start, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_snow3g_more, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_enc_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_enc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_dec_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_dec1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_sms4_enc_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_sms4_enc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_sms4_dec_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_sms4_dec1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_des3_enc_cbc, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_kas_enc_cbc, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_des3_enc, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_kas_enc, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_des3_dec_cbc, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_des3_dec, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_camellia_fl, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_camellia_flinv, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_camellia_round, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_hsh_startsha1_compat, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_hsh_startmd5, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_hsh_startsha256, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_hsh_startsha, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_hsh_startsha512, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_read_addr0, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_write_addr0, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_read64_addr0, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_write64_addr0, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_read_addr1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_write_addr1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_read64_addr1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_llm_write64_addr1, void, env, i64)
/* microMIPS functions */
DEF_HELPER_4(lwm, void, env, tl, tl, i32)
DEF_HELPER_4(swm, void, env, tl, tl, i32)
@@ -195,6 +254,8 @@ DEF_HELPER_1(rdhwr_cc, tl, env)
DEF_HELPER_1(rdhwr_ccres, tl, env)
DEF_HELPER_1(rdhwr_performance, tl, env)
DEF_HELPER_1(rdhwr_xnp, tl, env)
DEF_HELPER_1(rdhwr_chord, tl, env)
DEF_HELPER_1(rdhwr_cvmcount, tl, env)
DEF_HELPER_2(pmon, void, env, int)
DEF_HELPER_1(wait, void, env)

3
target/mips/internal.h
View File

@@ -93,6 +93,9 @@ extern const int mips_defs_number;
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
QTree *mips_octeon_llm_tree_new(void);
uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr);
void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value);
#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)

94
target/mips/system/machine.c
View File

@@ -131,6 +131,69 @@ static const VMStateDescription vmstate_octeon_multiplier_tc = {
}
};
typedef struct OcteonLLMTreePutData {
QEMUFile *f;
} OcteonLLMTreePutData;
static gboolean put_octeon_llm_tree_entry(gpointer key, gpointer value,
gpointer user_data)
{
OcteonLLMTreePutData *data = user_data;
qemu_put_be64(data->f, *(uint64_t *)key);
qemu_put_be64(data->f, *(uint64_t *)value);
return false;
}
static int put_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
QTree *tree = *(QTree **)pv;
OcteonLLMTreePutData data = { .f = f };
uint32_t nnodes = tree ? q_tree_nnodes(tree) : 0;
qemu_put_be32(f, nnodes);
if (tree) {
q_tree_foreach(tree, put_octeon_llm_tree_entry, &data);
}
return 0;
}
static int get_octeon_llm_tree(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
QTree **treep = pv;
uint32_t nnodes = qemu_get_be32(f);
if (*treep) {
q_tree_destroy(*treep);
}
*treep = mips_octeon_llm_tree_new();
for (uint32_t i = 0; i < nnodes; i++) {
uint64_t addr = qemu_get_be64(f);
uint64_t value = qemu_get_be64(f);
mips_octeon_llm_store(treep, addr, value);
}
return 0;
}
static const VMStateInfo vmstate_info_octeon_llm_tree = {
.name = "octeon_llm_tree",
.get = get_octeon_llm_tree,
.put = put_octeon_llm_tree,
};
#define VMSTATE_OCTEON_LLM_TREE(_f, _s) { \
.name = stringify(_f), \
.version_id = 1, \
.info = &vmstate_info_octeon_llm_tree, \
.offset = vmstate_offset_pointer(_s, _f, QTree), \
}
/* MVP state */
static const VMStateDescription vmstate_mvp = {
@@ -279,6 +342,36 @@ static const VMStateDescription mips_vmstate_octeon_multiplier = {
}
};
static const VMStateDescription mips_vmstate_octeon_crypto = {
.name = "cpu/octeon_crypto",
.version_id = 1,
.minimum_version_id = 1,
.needed = mips_octeon_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8),
VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3),
VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU),
VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4),
VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU),
VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2),
VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU),
VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU),
VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU),
VMSTATE_UINT64(env.octeon_crypto.chord, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.octeon_crypto.llm_data, MIPSCPU, 2),
VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm36, MIPSCPU),
VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm64, MIPSCPU),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
.version_id = 21,
@@ -396,6 +489,7 @@ const VMStateDescription vmstate_mips_cpu = {
.subsections = (const VMStateDescription * const []) {
&mips_vmstate_timer,
&mips_vmstate_octeon_multiplier,
&mips_vmstate_octeon_crypto,
NULL
}
};

1
target/mips/tcg/meson.build
View File

@@ -18,6 +18,7 @@ mips_ss.add(files(
'lmmi_helper.c',
'msa_helper.c',
'msa_translate.c',
'octeon_crypto.c',
'op_helper.c',
'rel6_translate.c',
'translate.c',

213
target/mips/tcg/octeon.decode
View File

@@ -97,3 +97,216 @@ LBUX 011111 ..... ..... ..... 00110 001010 @lx
LWUX 011111 ..... ..... ..... 10000 001010 @lx
LBX 011111 ..... ..... ..... 10110 001010 @lx
LDX 011111 ..... ..... ..... 01000 001010 @lx
# Selector-driven DMFC2/DMTC2 interfaces for Octeon COP2 engines.
&cp2 rt
{
[
CVM_MF_HSH_IV0 010010 00001 rt:5 0000 0000 0100 1000 &cp2
CVM_MF_HSH_IV1 010010 00001 rt:5 0000 0000 0100 1001 &cp2
CVM_MF_HSH_IV2 010010 00001 rt:5 0000 0000 0100 1010 &cp2
CVM_MF_HSH_IV3 010010 00001 rt:5 0000 0000 0100 1011 &cp2
CVM_MF_HSH_DAT0 010010 00001 rt:5 0000 0000 0100 0000 &cp2
CVM_MF_HSH_DAT1 010010 00001 rt:5 0000 0000 0100 0001 &cp2
CVM_MF_HSH_DAT2 010010 00001 rt:5 0000 0000 0100 0010 &cp2
CVM_MF_HSH_DAT3 010010 00001 rt:5 0000 0000 0100 0011 &cp2
CVM_MF_HSH_DAT4 010010 00001 rt:5 0000 0000 0100 0100 &cp2
CVM_MF_HSH_DAT5 010010 00001 rt:5 0000 0000 0100 0101 &cp2
CVM_MF_HSH_DAT6 010010 00001 rt:5 0000 0000 0100 0110 &cp2
CVM_MF_SHA3_DAT24 010010 00001 rt:5 0000 0000 0101 0000 &cp2
CVM_MF_3DES_KEY0 010010 00001 rt:5 0000 0000 1000 0000 &cp2
CVM_MF_3DES_KEY1 010010 00001 rt:5 0000 0000 1000 0001 &cp2
CVM_MF_3DES_KEY2 010010 00001 rt:5 0000 0000 1000 0010 &cp2
CVM_MF_3DES_IV 010010 00001 rt:5 0000 0000 1000 0100 &cp2
CVM_MF_3DES_RESULT 010010 00001 rt:5 0000 0000 1000 1000 &cp2
CVM_MF_KAS_RESULT 010010 00001 rt:5 0000 0000 1001 1000 &cp2
CVM_MF_AES_RESINP0 010010 00001 rt:5 0000 0001 0000 0000 &cp2
CVM_MF_AES_RESINP1 010010 00001 rt:5 0000 0001 0000 0001 &cp2
CVM_MF_AES_IV0 010010 00001 rt:5 0000 0001 0000 0010 &cp2
CVM_MF_AES_IV1 010010 00001 rt:5 0000 0001 0000 0011 &cp2
CVM_MF_AES_KEY0 010010 00001 rt:5 0000 0001 0000 0100 &cp2
CVM_MF_AES_KEY1 010010 00001 rt:5 0000 0001 0000 0101 &cp2
CVM_MF_AES_KEY2 010010 00001 rt:5 0000 0001 0000 0110 &cp2
CVM_MF_AES_KEY3 010010 00001 rt:5 0000 0001 0000 0111 &cp2
CVM_MF_AES_KEYLENGTH 010010 00001 rt:5 0000 0001 0001 0000 &cp2
CVM_MF_AES_INP0 010010 00001 rt:5 0000 0001 0001 0001 &cp2
CVM_MF_CRC_POLYNOMIAL 010010 00001 rt:5 0000 0010 0000 0000 &cp2
CVM_MF_CRC_IV 010010 00001 rt:5 0000 0010 0000 0001 &cp2
CVM_MF_CRC_LEN 010010 00001 rt:5 0000 0010 0000 0010 &cp2
CVM_MF_CRC_IV_REFLECT 010010 00001 rt:5 0000 0010 0000 0011 &cp2
CVM_MF_GFM_MUL_REFLECT0 010010 00001 rt:5 0000 0000 0101 1000 &cp2
CVM_MF_GFM_MUL_REFLECT1 010010 00001 rt:5 0000 0000 0101 1001 &cp2
CVM_MF_GFM_RESINP_REFLECT0 010010 00001 rt:5 0000 0000 0101 1010 &cp2
CVM_MF_GFM_RESINP_REFLECT1 010010 00001 rt:5 0000 0000 0101 1011 &cp2
CVM_MF_HSH_DATW0 010010 00001 rt:5 0000 0010 0100 0000 &cp2
CVM_MF_HSH_DATW1 010010 00001 rt:5 0000 0010 0100 0001 &cp2
CVM_MF_HSH_DATW2 010010 00001 rt:5 0000 0010 0100 0010 &cp2
CVM_MF_HSH_DATW3 010010 00001 rt:5 0000 0010 0100 0011 &cp2
CVM_MF_HSH_DATW4 010010 00001 rt:5 0000 0010 0100 0100 &cp2
CVM_MF_HSH_DATW5 010010 00001 rt:5 0000 0010 0100 0101 &cp2
CVM_MF_HSH_DATW6 010010 00001 rt:5 0000 0010 0100 0110 &cp2
CVM_MF_HSH_DATW7 010010 00001 rt:5 0000 0010 0100 0111 &cp2
CVM_MF_HSH_DATW8 010010 00001 rt:5 0000 0010 0100 1000 &cp2
CVM_MF_HSH_DATW9 010010 00001 rt:5 0000 0010 0100 1001 &cp2
CVM_MF_HSH_DATW10 010010 00001 rt:5 0000 0010 0100 1010 &cp2
CVM_MF_HSH_DATW11 010010 00001 rt:5 0000 0010 0100 1011 &cp2
CVM_MF_HSH_DATW12 010010 00001 rt:5 0000 0010 0100 1100 &cp2
CVM_MF_HSH_DATW13 010010 00001 rt:5 0000 0010 0100 1101 &cp2
CVM_MF_HSH_DATW14 010010 00001 rt:5 0000 0010 0100 1110 &cp2
CVM_MF_HSH_DATW15 010010 00001 rt:5 0000 0010 0100 1111 &cp2
CVM_MF_HSH_IVW0 010010 00001 rt:5 0000 0010 0101 0000 &cp2
CVM_MF_HSH_IVW1 010010 00001 rt:5 0000 0010 0101 0001 &cp2
CVM_MF_HSH_IVW2 010010 00001 rt:5 0000 0010 0101 0010 &cp2
CVM_MF_HSH_IVW3 010010 00001 rt:5 0000 0010 0101 0011 &cp2
CVM_MF_HSH_IVW4 010010 00001 rt:5 0000 0010 0101 0100 &cp2
CVM_MF_HSH_IVW5 010010 00001 rt:5 0000 0010 0101 0101 &cp2
CVM_MF_HSH_IVW6 010010 00001 rt:5 0000 0010 0101 0110 &cp2
CVM_MF_HSH_IVW7 010010 00001 rt:5 0000 0010 0101 0111 &cp2
CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 1000 &cp2
CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 1001 &cp2
CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 1010 &cp2
CVM_MF_GFM_RESINP1 010010 00001 rt:5 0000 0010 0101 1011 &cp2
CVM_MF_GFM_POLY 010010 00001 rt:5 0000 0010 0101 1110 &cp2
CVM_MF_CHORD 010010 00001 rt:5 0000 0100 0000 0000 &cp2
CVM_MF_LLM_DATA0 010010 00001 rt:5 0000 0100 0000 0010 &cp2
CVM_MF_LLM_DATA1 010010 00001 rt:5 0000 0100 0000 1010 &cp2
CVM_MT_HSH_DAT0 010010 00101 rt:5 0000 0000 0100 0000 &cp2
CVM_MT_HSH_DAT1 010010 00101 rt:5 0000 0000 0100 0001 &cp2
CVM_MT_HSH_DAT2 010010 00101 rt:5 0000 0000 0100 0010 &cp2
CVM_MT_HSH_DAT3 010010 00101 rt:5 0000 0000 0100 0011 &cp2
CVM_MT_HSH_DAT4 010010 00101 rt:5 0000 0000 0100 0100 &cp2
CVM_MT_HSH_DAT5 010010 00101 rt:5 0000 0000 0100 0101 &cp2
CVM_MT_HSH_DAT6 010010 00101 rt:5 0000 0000 0100 0110 &cp2
CVM_MT_HSH_IV0 010010 00101 rt:5 0000 0000 0100 1000 &cp2
CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 1001 &cp2
CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 1010 &cp2
CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 1011 &cp2
CVM_MT_SHA3_DAT24 010010 00101 rt:5 0000 0000 0101 0000 &cp2
CVM_MT_SHA3_DAT15 010010 00101 rt:5 0000 0000 0101 0001 &cp2
# Cavium SDK code uses 0x0057 as a STARTSHA1 compatibility alias.
CVM_MT_HSH_STARTSHA1_COMPAT 010010 00101 rt:5 0000 0000 0101 0111 &cp2
CVM_MT_GFM_MUL_REFLECT0 010010 00101 rt:5 0000 0000 0101 1000 &cp2
CVM_MT_GFM_MUL_REFLECT1 010010 00101 rt:5 0000 0000 0101 1001 &cp2
CVM_MT_GFM_XOR0_REFLECT 010010 00101 rt:5 0000 0000 0101 1100 &cp2
CVM_MT_3DES_KEY0 010010 00101 rt:5 0000 0000 1000 0000 &cp2
CVM_MT_3DES_KEY1 010010 00101 rt:5 0000 0000 1000 0001 &cp2
CVM_MT_3DES_KEY2 010010 00101 rt:5 0000 0000 1000 0010 &cp2
CVM_MT_3DES_IV 010010 00101 rt:5 0000 0000 1000 0100 &cp2
CVM_MT_3DES_RESULT 010010 00101 rt:5 0000 0000 1001 1000 &cp2
CVM_MT_AES_RESINP0 010010 00101 rt:5 0000 0001 0000 0000 &cp2
CVM_MT_AES_RESINP1 010010 00101 rt:5 0000 0001 0000 0001 &cp2
CVM_MT_AES_IV0 010010 00101 rt:5 0000 0001 0000 0010 &cp2
CVM_MT_AES_IV1 010010 00101 rt:5 0000 0001 0000 0011 &cp2
CVM_MT_AES_KEY0 010010 00101 rt:5 0000 0001 0000 0100 &cp2
CVM_MT_AES_KEY1 010010 00101 rt:5 0000 0001 0000 0101 &cp2
CVM_MT_AES_KEY2 010010 00101 rt:5 0000 0001 0000 0110 &cp2
CVM_MT_AES_KEY3 010010 00101 rt:5 0000 0001 0000 0111 &cp2
CVM_MT_AES_ENC_CBC0 010010 00101 rt:5 0000 0001 0000 1000 &cp2
CVM_MT_AES_ENC0 010010 00101 rt:5 0000 0001 0000 1010 &cp2
CVM_MT_AES_DEC_CBC0 010010 00101 rt:5 0000 0001 0000 1100 &cp2
CVM_MT_AES_DEC0 010010 00101 rt:5 0000 0001 0000 1110 &cp2
CVM_MT_AES_KEYLENGTH 010010 00101 rt:5 0000 0001 0001 0000 &cp2
CVM_MT_CAMELLIA_FL 010010 00101 rt:5 0000 0001 0001 0101 &cp2
CVM_MT_CAMELLIA_FLINV 010010 00101 rt:5 0000 0001 0001 0110 &cp2
CVM_MT_CRC_IV 010010 00101 rt:5 0000 0010 0000 0001 &cp2
CVM_MT_CRC_IV_REFLECT 010010 00101 rt:5 0000 0010 0001 0001 &cp2
CVM_MT_CRC_BYTE 010010 00101 rt:5 0000 0010 0000 0100 &cp2
CVM_MT_CRC_HALF 010010 00101 rt:5 0000 0010 0000 0101 &cp2
CVM_MT_CRC_WORD 010010 00101 rt:5 0000 0010 0000 0110 &cp2
CVM_MT_CRC_BYTE_REFLECT 010010 00101 rt:5 0000 0010 0001 0100 &cp2
CVM_MT_CRC_HALF_REFLECT 010010 00101 rt:5 0000 0010 0001 0101 &cp2
CVM_MT_CRC_WORD_REFLECT 010010 00101 rt:5 0000 0010 0001 0110 &cp2
CVM_MT_HSH_DATW0 010010 00101 rt:5 0000 0010 0100 0000 &cp2
CVM_MT_HSH_DATW1 010010 00101 rt:5 0000 0010 0100 0001 &cp2
CVM_MT_HSH_DATW2 010010 00101 rt:5 0000 0010 0100 0010 &cp2
CVM_MT_HSH_DATW3 010010 00101 rt:5 0000 0010 0100 0011 &cp2
CVM_MT_HSH_DATW4 010010 00101 rt:5 0000 0010 0100 0100 &cp2
CVM_MT_HSH_DATW5 010010 00101 rt:5 0000 0010 0100 0101 &cp2
CVM_MT_HSH_DATW6 010010 00101 rt:5 0000 0010 0100 0110 &cp2
CVM_MT_HSH_DATW7 010010 00101 rt:5 0000 0010 0100 0111 &cp2
CVM_MT_HSH_DATW8 010010 00101 rt:5 0000 0010 0100 1000 &cp2
CVM_MT_HSH_DATW9 010010 00101 rt:5 0000 0010 0100 1001 &cp2
CVM_MT_HSH_DATW10 010010 00101 rt:5 0000 0010 0100 1010 &cp2
CVM_MT_HSH_DATW11 010010 00101 rt:5 0000 0010 0100 1011 &cp2
CVM_MT_HSH_DATW12 010010 00101 rt:5 0000 0010 0100 1100 &cp2
CVM_MT_HSH_DATW13 010010 00101 rt:5 0000 0010 0100 1101 &cp2
CVM_MT_HSH_DATW14 010010 00101 rt:5 0000 0010 0100 1110 &cp2
CVM_MT_HSH_DATW15 010010 00101 rt:5 0000 0010 0100 1111 &cp2
CVM_MT_HSH_IVW0 010010 00101 rt:5 0000 0010 0101 0000 &cp2
CVM_MT_HSH_IVW1 010010 00101 rt:5 0000 0010 0101 0001 &cp2
CVM_MT_HSH_IVW2 010010 00101 rt:5 0000 0010 0101 0010 &cp2
CVM_MT_HSH_IVW3 010010 00101 rt:5 0000 0010 0101 0011 &cp2
CVM_MT_HSH_IVW4 010010 00101 rt:5 0000 0010 0101 0100 &cp2
CVM_MT_HSH_IVW5 010010 00101 rt:5 0000 0010 0101 0101 &cp2
CVM_MT_HSH_IVW6 010010 00101 rt:5 0000 0010 0101 0110 &cp2
CVM_MT_HSH_IVW7 010010 00101 rt:5 0000 0010 0101 0111 &cp2
CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 1000 &cp2
CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 1001 &cp2
CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 1010 &cp2
CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 1011 &cp2
CVM_MT_GFM_XOR0 010010 00101 rt:5 0000 0010 0101 1100 &cp2
CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 1110 &cp2
CVM_MT_SHA3_XORDAT0 010010 00101 rt:5 0000 0010 1100 0000 &cp2
CVM_MT_SHA3_XORDAT1 010010 00101 rt:5 0000 0010 1100 0001 &cp2
CVM_MT_SHA3_XORDAT2 010010 00101 rt:5 0000 0010 1100 0010 &cp2
CVM_MT_SHA3_XORDAT3 010010 00101 rt:5 0000 0010 1100 0011 &cp2
CVM_MT_SHA3_XORDAT4 010010 00101 rt:5 0000 0010 1100 0100 &cp2
CVM_MT_SHA3_XORDAT5 010010 00101 rt:5 0000 0010 1100 0101 &cp2
CVM_MT_SHA3_XORDAT6 010010 00101 rt:5 0000 0010 1100 0110 &cp2
CVM_MT_SHA3_XORDAT7 010010 00101 rt:5 0000 0010 1100 0111 &cp2
CVM_MT_SHA3_XORDAT8 010010 00101 rt:5 0000 0010 1100 1000 &cp2
CVM_MT_SHA3_XORDAT9 010010 00101 rt:5 0000 0010 1100 1001 &cp2
CVM_MT_SHA3_XORDAT10 010010 00101 rt:5 0000 0010 1100 1010 &cp2
CVM_MT_SHA3_XORDAT11 010010 00101 rt:5 0000 0010 1100 1011 &cp2
CVM_MT_SHA3_XORDAT12 010010 00101 rt:5 0000 0010 1100 1100 &cp2
CVM_MT_SHA3_XORDAT13 010010 00101 rt:5 0000 0010 1100 1101 &cp2
CVM_MT_SHA3_XORDAT14 010010 00101 rt:5 0000 0010 1100 1110 &cp2
CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 1111 &cp2
CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 0000 &cp2
CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 0001 &cp2
CVM_MT_LLM_READ_ADDR0 010010 00101 rt:5 0000 0100 0000 0000 &cp2
CVM_MT_LLM_WRITE_ADDR0 010010 00101 rt:5 0000 0100 0000 0001 &cp2
CVM_MT_LLM_DATA0 010010 00101 rt:5 0000 0100 0000 0010 &cp2
CVM_MT_LLM_READ64_ADDR0 010010 00101 rt:5 0000 0100 0000 0100 &cp2
CVM_MT_LLM_WRITE64_ADDR0 010010 00101 rt:5 0000 0100 0000 0101 &cp2
CVM_MT_LLM_READ_ADDR1 010010 00101 rt:5 0000 0100 0000 1000 &cp2
CVM_MT_LLM_WRITE_ADDR1 010010 00101 rt:5 0000 0100 0000 1001 &cp2
CVM_MT_LLM_DATA1 010010 00101 rt:5 0000 0100 0000 1010 &cp2
CVM_MT_LLM_READ64_ADDR1 010010 00101 rt:5 0000 0100 0000 1100 &cp2
CVM_MT_LLM_WRITE64_ADDR1 010010 00101 rt:5 0000 0100 0000 1101 &cp2
CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 0010 &cp2
CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 0111 &cp2
CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 1000 &cp2
CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 0111 &cp2
CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 1000 &cp2
CVM_MT_AES_ENC_CBC1 010010 00101 rt:5 0011 0001 0000 1001 &cp2
CVM_MT_AES_ENC1 010010 00101 rt:5 0011 0001 0000 1011 &cp2
CVM_MT_AES_DEC_CBC1 010010 00101 rt:5 0011 0001 0000 1101 &cp2
CVM_MT_AES_DEC1 010010 00101 rt:5 0011 0001 0000 1111 &cp2
CVM_MT_CAMELLIA_ROUND 010010 00101 rt:5 0011 0001 0001 0100 &cp2
CVM_MT_SMS4_ENC_CBC1 010010 00101 rt:5 0011 0001 0001 1001 &cp2
CVM_MT_SMS4_ENC1 010010 00101 rt:5 0011 0001 0001 1011 &cp2
CVM_MT_SMS4_DEC_CBC1 010010 00101 rt:5 0011 0001 0001 1101 &cp2
CVM_MT_SMS4_DEC1 010010 00101 rt:5 0011 0001 0001 1111 &cp2
CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 0111 &cp2
CVM_MT_SNOW3G_START 010010 00101 rt:5 0100 0000 0100 1101 &cp2
CVM_MT_SNOW3G_MORE 010010 00101 rt:5 0100 0000 0100 1110 &cp2
CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 1111 &cp2
CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 0010 &cp2
CVM_MT_ZUC_START 010010 00101 rt:5 0100 0000 0101 0101 &cp2
CVM_MT_ZUC_MORE 010010 00101 rt:5 0100 0000 0101 0110 &cp2
CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 0111 &cp2
CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 1101 &cp2
CVM_MT_3DES_ENC_CBC 010010 00101 rt:5 0100 0000 1000 1000 &cp2
CVM_MT_KAS_ENC_CBC 010010 00101 rt:5 0100 0000 1000 1001 &cp2
CVM_MT_3DES_ENC 010010 00101 rt:5 0100 0000 1000 1010 &cp2
CVM_MT_KAS_ENC 010010 00101 rt:5 0100 0000 1000 1011 &cp2
CVM_MT_3DES_DEC_CBC 010010 00101 rt:5 0100 0000 1000 1100 &cp2
CVM_MT_3DES_DEC 010010 00101 rt:5 0100 0000 1000 1110 &cp2
CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 0000 &cp2
CVM_MT_CRC_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 0000 &cp2
CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 1111 &cp2
CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 1101 &cp2
]
CP2_Undef 010010 ----- ----- ---- ---- ---- ----
}

2310
target/mips/tcg/octeon_crypto.c Normal file
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File diff suppressed because it is too large Load Diff

396
target/mips/tcg/octeon_translate.c
View File

@@ -13,6 +13,402 @@
/* Include the auto-generated decoder. */
#include "decode-octeon.c.inc"
#define OCTEON_CRYPTO_OFFSET(FIELD) \
offsetof(CPUMIPSState, octeon_crypto.FIELD)
#define CP2_MF_I64(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mf_i64, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MF_S32(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mf_s32, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MF_U16(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mf_u16, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MF_U8(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mf_u8, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MF_HSH_PAIR(NAME, FIELD, INDEX) \
TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
#define CP2_MF_HELPER(NAME, SUFFIX) \
TRANS(NAME, trans_octeon_cp2_mf_helper, \
gen_helper_octeon_cp2_mf_ ## SUFFIX)
#define CP2_MT_I64(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mt_i64, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MT_U32(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mt_u32, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MT_U16(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mt_u16, OCTEON_CRYPTO_OFFSET(FIELD))
#define CP2_MT_U8_MASKED(NAME, FIELD, MASK) \
TRANS(NAME, trans_octeon_cp2_mt_u8_masked, \
OCTEON_CRYPTO_OFFSET(FIELD), MASK)
#define CP2_MT_HSH_PAIR(NAME, FIELD, INDEX) \
TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \
OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1]))
#define CP2_MT_HELPER(NAME, SUFFIX) \
TRANS(NAME, trans_octeon_cp2_mt_helper, \
gen_helper_octeon_cp2_mt_ ## SUFFIX)
#define CP2_MT_HELPER_ENV(NAME, SUFFIX) \
TRANS(NAME, trans_octeon_cp2_mt_helper_env, \
gen_helper_octeon_cp2_mt_ ## SUFFIX)
#define CP2_MT_XOR_I64(NAME, FIELD) \
TRANS(NAME, trans_octeon_cp2_mt_xor_i64, OCTEON_CRYPTO_OFFSET(FIELD))
#define OCTEON_LO32_OFFSET (HOST_BIG_ENDIAN ? 4 : 0)
static bool trans_CP2_Undef(DisasContext *ctx, arg_CP2_Undef *a)
{
generate_exception_err(ctx, EXCP_CpU, 2);
return true;
}
static bool trans_octeon_cp2_mf_i64(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
tcg_gen_ld_i64(value, tcg_env, offset);
gen_store_gpr(value, a->rt);
return true;
}
static bool trans_octeon_cp2_mf_s32(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
tcg_gen_ld32s_i64(value, tcg_env, offset);
gen_store_gpr(value, a->rt);
return true;
}
static bool trans_octeon_cp2_mf_u16(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
tcg_gen_ld16u_i64(value, tcg_env, offset);
gen_store_gpr(value, a->rt);
return true;
}
static bool trans_octeon_cp2_mf_u8(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
tcg_gen_ld8u_i64(value, tcg_env, offset);
gen_store_gpr(value, a->rt);
return true;
}
static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *ctx, arg_cp2 *a,
int hi_offset, int lo_offset)
{
TCGv_i64 hi = tcg_temp_new_i64();
TCGv_i64 lo = tcg_temp_new_i64();
tcg_gen_ld_i64(hi, tcg_env, hi_offset);
tcg_gen_ld_i64(lo, tcg_env, lo_offset);
tcg_gen_concat32_i64(lo, lo, hi);
gen_store_gpr(lo, a->rt);
return true;
}
static bool trans_octeon_cp2_mf_helper(DisasContext *ctx, arg_cp2 *a,
void (*gen_helper)(TCGv_i64, TCGv_env))
{
TCGv_i64 value = tcg_temp_new_i64();
gen_helper(value, tcg_env);
gen_store_gpr(value, a->rt);
return true;
}
static bool trans_octeon_cp2_mt_i64(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_st_i64(value, tcg_env, offset);
return true;
}
static bool trans_octeon_cp2_mt_u32(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_st32_i64(value, tcg_env, offset);
return true;
}
static bool trans_octeon_cp2_mt_u16(DisasContext *ctx, arg_cp2 *a, int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_st16_i64(value, tcg_env, offset);
return true;
}
static bool trans_octeon_cp2_mt_u8_masked(DisasContext *ctx, arg_cp2 *a,
int offset, uint8_t mask)
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_andi_i64(value, value, mask);
tcg_gen_st8_i64(value, tcg_env, offset);
return true;
}
static bool trans_octeon_cp2_mt_hsh_pair(DisasContext *ctx, arg_cp2 *a,
int hi_offset, int lo_offset)
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_st32_i64(value, tcg_env, lo_offset + OCTEON_LO32_OFFSET);
tcg_gen_shri_i64(value, value, 32);
tcg_gen_st32_i64(value, tcg_env, hi_offset + OCTEON_LO32_OFFSET);
return true;
}
static bool trans_octeon_cp2_mt_xor_i64(DisasContext *ctx, arg_cp2 *a,
int offset)
{
TCGv_i64 value = tcg_temp_new_i64();
TCGv_i64 old = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
tcg_gen_ld_i64(old, tcg_env, offset);
tcg_gen_xor_i64(old, old, value);
tcg_gen_st_i64(old, tcg_env, offset);
return true;
}
static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a,
void (*gen_helper)(TCGv_env, TCGv_i64))
{
TCGv_i64 value = tcg_temp_new_i64();
gen_load_gpr(value, a->rt);
gen_helper(tcg_env, value);
return true;
}
static bool trans_octeon_cp2_mt_helper_env(DisasContext *ctx, arg_cp2 *a,
void (*gen_helper)(TCGv_env))
{
gen_helper(tcg_env);
return true;
}
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT3, hsh_dat, 3);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT4, hsh_dat, 4);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT5, hsh_dat, 5);
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT6, hsh_dat, 6);
CP2_MF_HSH_PAIR(CVM_MF_HSH_IV0, hsh_iv, 0);
CP2_MF_HSH_PAIR(CVM_MF_HSH_IV1, hsh_iv, 1);
CP2_MF_HSH_PAIR(CVM_MF_HSH_IV2, hsh_iv, 2);
CP2_MF_HSH_PAIR(CVM_MF_HSH_IV3, hsh_iv, 3);
CP2_MF_I64(CVM_MF_3DES_KEY0, des3_key[0]);
CP2_MF_I64(CVM_MF_3DES_KEY1, des3_key[1]);
CP2_MF_I64(CVM_MF_3DES_KEY2, des3_key[2]);
CP2_MF_I64(CVM_MF_3DES_IV, des3_iv);
CP2_MF_I64(CVM_MF_3DES_RESULT, des3_result);
CP2_MF_I64(CVM_MF_KAS_RESULT, des3_result);
CP2_MF_I64(CVM_MF_AES_RESINP0, aes_resinp[0]);
CP2_MF_I64(CVM_MF_AES_RESINP1, aes_resinp[1]);
CP2_MF_I64(CVM_MF_AES_IV0, aes_iv[0]);
CP2_MF_I64(CVM_MF_AES_IV1, aes_iv[1]);
CP2_MF_I64(CVM_MF_AES_KEY0, aes_key[0]);
CP2_MF_I64(CVM_MF_AES_KEY1, aes_key[1]);
CP2_MF_I64(CVM_MF_AES_KEY2, aes_key[2]);
CP2_MF_I64(CVM_MF_AES_KEY3, aes_key[3]);
CP2_MF_U8(CVM_MF_AES_KEYLENGTH, aes_keylen);
CP2_MF_I64(CVM_MF_AES_INP0, aes_resinp[0]);
CP2_MF_S32(CVM_MF_CRC_POLYNOMIAL, crc_poly);
CP2_MF_S32(CVM_MF_CRC_IV, crc_iv);
CP2_MF_U8(CVM_MF_CRC_LEN, crc_len);
CP2_MF_I64(CVM_MF_GFM_MUL0, gfm_mul[0]);
CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]);
CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]);
CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]);
CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly);
CP2_MF_I64(CVM_MF_CHORD, chord);
CP2_MF_I64(CVM_MF_LLM_DATA0, llm_data[0]);
CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]);
CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24);
CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0);
CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1);
CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0);
CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1);
CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]);
CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]);
CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]);
CP2_MF_I64(CVM_MF_HSH_DATW3, hsh_dat[3]);
CP2_MF_I64(CVM_MF_HSH_DATW4, hsh_dat[4]);
CP2_MF_I64(CVM_MF_HSH_DATW5, hsh_dat[5]);
CP2_MF_I64(CVM_MF_HSH_DATW6, hsh_dat[6]);
CP2_MF_I64(CVM_MF_HSH_DATW7, hsh_dat[7]);
CP2_MF_I64(CVM_MF_HSH_DATW8, hsh_dat[8]);
CP2_MF_I64(CVM_MF_HSH_DATW9, hsh_dat[9]);
CP2_MF_I64(CVM_MF_HSH_DATW10, hsh_dat[10]);
CP2_MF_I64(CVM_MF_HSH_DATW11, hsh_dat[11]);
CP2_MF_I64(CVM_MF_HSH_DATW12, hsh_dat[12]);
CP2_MF_I64(CVM_MF_HSH_DATW13, hsh_dat[13]);
CP2_MF_I64(CVM_MF_HSH_DATW14, hsh_dat[14]);
CP2_MF_I64(CVM_MF_HSH_DATW15, hsh_dat[15]);
CP2_MF_I64(CVM_MF_HSH_IVW0, hsh_iv[0]);
CP2_MF_I64(CVM_MF_HSH_IVW1, hsh_iv[1]);
CP2_MF_I64(CVM_MF_HSH_IVW2, hsh_iv[2]);
CP2_MF_I64(CVM_MF_HSH_IVW3, hsh_iv[3]);
CP2_MF_I64(CVM_MF_HSH_IVW4, hsh_iv[4]);
CP2_MF_I64(CVM_MF_HSH_IVW5, hsh_iv[5]);
CP2_MF_I64(CVM_MF_HSH_IVW6, hsh_iv[6]);
CP2_MF_I64(CVM_MF_HSH_IVW7, hsh_iv[7]);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT0, hsh_dat, 0);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT1, hsh_dat, 1);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT2, hsh_dat, 2);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT3, hsh_dat, 3);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT4, hsh_dat, 4);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT5, hsh_dat, 5);
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT6, hsh_dat, 6);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2);
CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3);
CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT0, gfm_mul_reflect0);
CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT1, gfm_mul_reflect1);
CP2_MT_HELPER(CVM_MT_GFM_XOR0_REFLECT, gfm_xor0_reflect);
CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]);
CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]);
CP2_MT_I64(CVM_MT_3DES_KEY2, des3_key[2]);
CP2_MT_I64(CVM_MT_3DES_IV, des3_iv);
CP2_MT_I64(CVM_MT_3DES_RESULT, des3_result);
CP2_MT_I64(CVM_MT_AES_RESINP0, aes_resinp[0]);
CP2_MT_I64(CVM_MT_AES_RESINP1, aes_resinp[1]);
CP2_MT_I64(CVM_MT_AES_IV0, aes_iv[0]);
CP2_MT_I64(CVM_MT_AES_IV1, aes_iv[1]);
CP2_MT_I64(CVM_MT_AES_KEY0, aes_key[0]);
CP2_MT_I64(CVM_MT_AES_KEY1, aes_key[1]);
CP2_MT_I64(CVM_MT_AES_KEY2, aes_key[2]);
CP2_MT_I64(CVM_MT_AES_KEY3, aes_key[3]);
CP2_MT_I64(CVM_MT_AES_ENC_CBC0, aes_resinp[0]);
CP2_MT_I64(CVM_MT_AES_ENC0, aes_resinp[0]);
CP2_MT_I64(CVM_MT_AES_DEC_CBC0, aes_resinp[0]);
CP2_MT_I64(CVM_MT_AES_DEC0, aes_resinp[0]);
CP2_MT_U8_MASKED(CVM_MT_AES_KEYLENGTH, aes_keylen, 3);
CP2_MT_U32(CVM_MT_CRC_IV, crc_iv);
CP2_MT_I64(CVM_MT_GFM_MUL0, gfm_mul[0]);
CP2_MT_I64(CVM_MT_GFM_MUL1, gfm_mul[1]);
CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]);
CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]);
CP2_MT_XOR_I64(CVM_MT_GFM_XOR0, gfm_resinp[0]);
CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly);
CP2_MT_I64(CVM_MT_LLM_DATA0, llm_data[0]);
CP2_MT_I64(CVM_MT_LLM_DATA1, llm_data[1]);
CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf);
CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly);
CP2_MT_HELPER(CVM_MT_CRC_POLYNOMIAL_REFLECT, crc_write_polynomial_reflect);
CP2_MT_HELPER(CVM_MT_CRC_IV_REFLECT, crc_write_iv_reflect);
CP2_MT_HELPER(CVM_MT_CRC_BYTE, crc_write_byte);
CP2_MT_HELPER(CVM_MT_CRC_HALF, crc_write_half);
CP2_MT_HELPER(CVM_MT_CRC_WORD, crc_write_word);
CP2_MT_HELPER(CVM_MT_CRC_BYTE_REFLECT, crc_write_byte_reflect);
CP2_MT_HELPER(CVM_MT_CRC_HALF_REFLECT, crc_write_half_reflect);
CP2_MT_HELPER(CVM_MT_CRC_WORD_REFLECT, crc_write_word_reflect);
CP2_MT_HELPER(CVM_MT_CRC_DWORD, crc_write_dword);
CP2_MT_HELPER(CVM_MT_CRC_VAR, crc_write_var);
CP2_MT_HELPER(CVM_MT_CRC_DWORD_REFLECT, crc_write_dword_reflect);
CP2_MT_HELPER(CVM_MT_CRC_VAR_REFLECT, crc_write_var_reflect);
CP2_MT_HELPER(CVM_MT_GFM_XORMUL1_REFLECT, gfm_xormul1_reflect);
CP2_MT_HELPER(CVM_MT_GFM_XORMUL1, gfm_xormul1);
CP2_MT_I64(CVM_MT_SHA3_DAT24, sha3_dat24);
CP2_MT_I64(CVM_MT_SHA3_DAT15, hsh_dat[15]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT0, sha3_dat[0]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT1, sha3_dat[1]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT2, sha3_dat[2]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT3, sha3_dat[3]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT4, sha3_dat[4]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT5, sha3_dat[5]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT6, sha3_dat[6]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT7, sha3_dat[7]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT8, sha3_dat[8]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT9, sha3_dat[9]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT10, sha3_dat[10]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT11, sha3_dat[11]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT12, sha3_dat[12]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT13, sha3_dat[13]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT14, sha3_dat[14]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT15, sha3_dat[15]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT16, sha3_dat[16]);
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT17, sha3_dat[17]);
CP2_MT_HELPER_ENV(CVM_MT_SHA3_STARTOP, sha3_startop);
CP2_MT_HELPER(CVM_MT_ZUC_START, zuc_start);
CP2_MT_HELPER(CVM_MT_ZUC_MORE, zuc_more);
CP2_MT_HELPER(CVM_MT_SNOW3G_START, snow3g_start);
CP2_MT_HELPER(CVM_MT_SNOW3G_MORE, snow3g_more);
CP2_MT_HELPER(CVM_MT_AES_ENC_CBC1, aes_enc_cbc1);
CP2_MT_HELPER(CVM_MT_AES_ENC1, aes_enc1);
CP2_MT_HELPER(CVM_MT_AES_DEC_CBC1, aes_dec_cbc1);
CP2_MT_HELPER(CVM_MT_AES_DEC1, aes_dec1);
CP2_MT_HELPER(CVM_MT_SMS4_ENC_CBC1, sms4_enc_cbc1);
CP2_MT_HELPER(CVM_MT_SMS4_ENC1, sms4_enc1);
CP2_MT_HELPER(CVM_MT_SMS4_DEC_CBC1, sms4_dec_cbc1);
CP2_MT_HELPER(CVM_MT_SMS4_DEC1, sms4_dec1);
CP2_MT_HELPER(CVM_MT_3DES_ENC_CBC, des3_enc_cbc);
CP2_MT_HELPER(CVM_MT_KAS_ENC_CBC, kas_enc_cbc);
CP2_MT_HELPER(CVM_MT_3DES_ENC, des3_enc);
CP2_MT_HELPER(CVM_MT_KAS_ENC, kas_enc);
CP2_MT_HELPER(CVM_MT_3DES_DEC_CBC, des3_dec_cbc);
CP2_MT_HELPER(CVM_MT_3DES_DEC, des3_dec);
CP2_MT_HELPER(CVM_MT_CAMELLIA_FL, camellia_fl);
CP2_MT_HELPER(CVM_MT_CAMELLIA_FLINV, camellia_flinv);
CP2_MT_HELPER(CVM_MT_CAMELLIA_ROUND, camellia_round);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat);
CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]);
CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]);
CP2_MT_I64(CVM_MT_HSH_DATW2, hsh_dat[2]);
CP2_MT_I64(CVM_MT_HSH_DATW3, hsh_dat[3]);
CP2_MT_I64(CVM_MT_HSH_DATW4, hsh_dat[4]);
CP2_MT_I64(CVM_MT_HSH_DATW5, hsh_dat[5]);
CP2_MT_I64(CVM_MT_HSH_DATW6, hsh_dat[6]);
CP2_MT_I64(CVM_MT_HSH_DATW7, hsh_dat[7]);
CP2_MT_I64(CVM_MT_HSH_DATW8, hsh_dat[8]);
CP2_MT_I64(CVM_MT_HSH_DATW9, hsh_dat[9]);
CP2_MT_I64(CVM_MT_HSH_DATW10, hsh_dat[10]);
CP2_MT_I64(CVM_MT_HSH_DATW11, hsh_dat[11]);
CP2_MT_I64(CVM_MT_HSH_DATW12, hsh_dat[12]);
CP2_MT_I64(CVM_MT_HSH_DATW13, hsh_dat[13]);
CP2_MT_I64(CVM_MT_HSH_DATW14, hsh_dat[14]);
CP2_MT_I64(CVM_MT_HSH_DATW15, hsh_dat[15]);
CP2_MT_I64(CVM_MT_HSH_IVW0, hsh_iv[0]);
CP2_MT_I64(CVM_MT_HSH_IVW1, hsh_iv[1]);
CP2_MT_I64(CVM_MT_HSH_IVW2, hsh_iv[2]);
CP2_MT_I64(CVM_MT_HSH_IVW3, hsh_iv[3]);
CP2_MT_I64(CVM_MT_HSH_IVW4, hsh_iv[4]);
CP2_MT_I64(CVM_MT_HSH_IVW5, hsh_iv[5]);
CP2_MT_I64(CVM_MT_HSH_IVW6, hsh_iv[6]);
CP2_MT_I64(CVM_MT_HSH_IVW7, hsh_iv[7]);
CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha);
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512);
CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0);
CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0);
CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0);
CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0);
CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1);
CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1);
CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1);
CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1);
static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
{
TCGv_i64 p;

19
target/mips/tcg/op_helper.c
View File

@@ -25,6 +25,7 @@
#include "exec/memop.h"
#include "fpu_helper.h"
#include "qemu/crc32c.h"
#include "qemu/timer.h"
#include <zlib.h>
static inline target_ulong bitswap(target_ulong v)
@@ -209,7 +210,7 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
{
if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1u << reg))) {
return;
}
do_raise_exception(env, EXCP_RI, pc);
@@ -255,6 +256,22 @@ target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
return (env->CP0_Config5 >> CP0C5_XNP) & 1;
}
target_ulong helper_rdhwr_chord(CPUMIPSState *env)
{
check_hwrena(env, 30, GETPC());
return env->octeon_crypto.chord;
}
target_ulong helper_rdhwr_cvmcount(CPUMIPSState *env)
{
check_hwrena(env, 31, GETPC());
#ifdef CONFIG_USER_ONLY
return cpu_get_host_ticks();
#else
return (uint32_t)cpu_mips_get_count(env);
#endif
}
void helper_pmon(CPUMIPSState *env, int function)
{
function /= 2;

19
target/mips/tcg/translate.c
View File

@@ -10925,6 +10925,25 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
}
break;
#endif
case 30:
if (!(ctx->insn_flags & INSN_OCTEON)) {
gen_reserved_instruction(ctx);
break;
}
gen_helper_rdhwr_chord(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 31:
if (!(ctx->insn_flags & INSN_OCTEON)) {
gen_reserved_instruction(ctx);
break;
}
translator_io_start(&ctx->base);
gen_helper_rdhwr_cvmcount(t0, tcg_env);
gen_store_gpr(t0, rt);
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
default: /* Invalid */
MIPS_INVAL("rdhwr");
gen_reserved_instruction(ctx);

2
target/sh4/op_helper.c
View File

@@ -488,7 +488,7 @@ void helper_ftrv(CPUSH4State *env, uint32_t n)
float32 p;
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
bank_vector = (env->sr & FPSCR_FR) ? 16 + n : n;
set_float_exception_flags(0, &env->fp_status);
for (i = 0 ; i < 4 ; i++) {
r[i] = float32_zero;

15
target/sh4/translate.c
View File

@@ -377,11 +377,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
goto do_illegal; \
}
#define CHECK_FPSCR_PR_1 \
if (!(ctx->tbflags & FPSCR_PR)) { \
goto do_illegal; \
}
#define CHECK_SH4A \
if (!(ctx->features & SH_FEATURE_SH4A)) { \
goto do_illegal; \
@@ -1740,22 +1735,22 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf0ed: /* fipr FVm,FVn */
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_1
CHECK_FPSCR_PR_0
{
TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
TCGv m = tcg_constant_i32(((ctx->opcode >> 8) & 3) << 2);
TCGv n = tcg_constant_i32(((ctx->opcode >> 10) & 3) << 2);
gen_helper_fipr(tcg_env, m, n);
return;
}
break;
case 0xf0fd: /* ftrv XMTRX,FVn */
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_1
CHECK_FPSCR_PR_0
{
if ((ctx->opcode & 0x0300) != 0x0100) {
goto do_illegal;
}
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
TCGv n = tcg_constant_i32(((ctx->opcode >> 10) & 3) << 2);
gen_helper_ftrv(tcg_env, n);
return;
}

216
tests/tcg/mips/user/isa/octeon/octeon-insns.c
View File

@@ -129,6 +129,43 @@ static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0,
return rd;
}
static uint64_t octeon_qmac_lo(uint64_t rs, uint64_t rt, uint64_t lo)
{
uint64_t rd;
asm volatile(
"move $8, %[rs]\n\t"
"move $9, %[rt]\n\t"
"mtlo %[lo]\n\t"
"mthi $0\n\t"
".word 0x710904d2\n\t" /* qmac.03 $8, $9 */
"mflo %[rd]\n\t"
: [rd] "=r" (rd)
: [rs] "r" (rs), [rt] "r" (rt), [lo] "r" (lo)
: "$8", "$9");
return rd;
}
static uint64_t octeon_qmacs_state(uint64_t rs, uint64_t rt, uint64_t lo)
{
uint64_t hi, rd;
asm volatile(
"move $8, %[rs]\n\t"
"move $9, %[rt]\n\t"
"mtlo %[lo]\n\t"
"mthi $0\n\t"
".word 0x71090012\n\t" /* qmacs.00 $8, $9 */
"mfhi %[hi]\n\t"
"mflo %[rd]\n\t"
: [hi] "=r" (hi), [rd] "=r" (rd)
: [rs] "r" (rs), [rt] "r" (rt), [lo] "r" (lo)
: "$8", "$9");
return ((hi & 1) << 32) | (rd & 0xffffffff);
}
static uint64_t octeon_vmm0_zeroes_mpl1(void)
{
uint64_t rd;
@@ -186,6 +223,166 @@ static uint64_t octeon_mtp0_zeroes_p1(void)
return rd;
}
static uint64_t octeon_cop2_key0_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80104\n\t" /* dmtc2 $8, AES_KEY0 selector */
".word 0x482a0104\n\t" /* dmfc2 $10, AES_KEY0 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_key2_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80106\n\t" /* dmtc2 $8, AES_KEY2 selector */
".word 0x482a0106\n\t" /* dmfc2 $10, AES_KEY2 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_key3_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80107\n\t" /* dmtc2 $8, AES_KEY3 selector */
".word 0x482a0107\n\t" /* dmfc2 $10, AES_KEY3 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_keylength_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80110\n\t" /* dmtc2 $8, AES_KEYLENGTH selector */
".word 0x482a0110\n\t" /* dmfc2 $10, AES_KEYLENGTH selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_hsh_dat0_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80040\n\t" /* dmtc2 $8, HSH_DAT0 selector */
".word 0x482a0040\n\t" /* dmfc2 $10, HSH_DAT0 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_crc_len_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a81202\n\t" /* dmtc2 $8, CRC_LEN selector */
".word 0x482a0202\n\t" /* dmfc2 $10, CRC_LEN selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_crc_poly_reflect_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a84210\n\t" /* dmtc2 $8, CRC_POLYNOMIAL_REFLECT selector */
".word 0x482a0200\n\t" /* dmfc2 $10, CRC_POLYNOMIAL selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_gfm_mul_reflect_write_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80058\n\t" /* dmtc2 $8, GFM_MUL_REFLECT0 selector */
".word 0x482a0258\n\t" /* dmfc2 $10, GFM_MUL0 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_cop2_gfm_mul_reflect_readback(uint64_t value)
{
uint64_t rd;
asm volatile(
"move $8, %[value]\n\t"
".word 0x48a80258\n\t" /* dmtc2 $8, GFM_MUL0 selector */
".word 0x482a0058\n\t" /* dmfc2 $10, GFM_MUL_REFLECT0 selector */
"move %[rd], $10\n\t"
: [rd] "=r" (rd)
: [value] "r" (value)
: "$8", "$10");
return rd;
}
static uint64_t octeon_rdhwr31_non_decreasing(void)
{
uint64_t first, second;
asm volatile(
".word 0x7c08f83b\n\t" /* rdhwr $8, $31 */
".word 0x7c09f83b\n\t" /* rdhwr $9, $31 */
"move %[first], $8\n\t"
"move %[second], $9\n\t"
: [first] "=r" (first), [second] "=r" (second)
:
: "$8", "$9");
return second >= first;
}
int main(void)
{
assert(octeon_baddu(0x123, 0x0f0) == 0x13);
@@ -195,10 +392,29 @@ int main(void)
assert(octeon_seq(0xabc, 0xdef) == 0);
assert(octeon_sne(0xabc, 0xabc) == 0);
assert(octeon_sne(0xabc, 0xdef) == 1);
assert(octeon_qmac_lo(0x0003000000000000ULL, 2, 1) == 13);
assert(octeon_qmacs_state(1, 1, 0x7ffffffe) == 0x17fffffffULL);
assert(octeon_qmacs_state(0x8000, 0x8000, 0) == 0x17fffffffULL);
assert(octeon_vmulu(5, 7, 11) == 46);
assert(octeon_vmm0(5, 13, 7, 11) == 59);
assert(octeon_vmm0_zeroes_mpl1() == 0);
assert(octeon_mtp0_zeroes_p1() == 0);
assert(octeon_cop2_key0_readback(0x1122334455667788ULL) ==
0x1122334455667788ULL);
assert(octeon_cop2_key2_readback(0x8877665544332211ULL) ==
0x8877665544332211ULL);
assert(octeon_cop2_key3_readback(0x0102030405060708ULL) ==
0x0102030405060708ULL);
assert(octeon_cop2_keylength_readback(0xa5) == 1);
assert(octeon_cop2_hsh_dat0_readback(0x0102030405060708ULL) ==
0x0102030405060708ULL);
assert(octeon_cop2_crc_len_readback(0xb5) == 5);
assert(octeon_cop2_crc_poly_reflect_readback(0x12345678) == 0x482c6a1e);
assert(octeon_cop2_gfm_mul_reflect_write_readback(
0x0123456789abcdefULL) == 0xf7b3d591e6a2c480ULL);
assert(octeon_cop2_gfm_mul_reflect_readback(
0xfedcba9876543210ULL) == 0x084c2a6e195d3b7fULL);
assert(octeon_rdhwr31_non_decreasing());
return 0;
}