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target/arm: Update SCR bits for Arm ARM M.a.a

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
2026-05-22 15:02:08 -07:00
committed by Peter Maydell
parent 697910f67f
commit 394c4db5cf
1 changed files with 11 additions and 0 deletions
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11
target/arm/cpu.h
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@@ -1820,6 +1820,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_AIEN (1ULL << 46)
#define SCR_GPF (1ULL << 48)
#define SCR_MECEN (1ULL << 49)
#define SCR_ENFPM (1ULL << 50)
#define SCR_TMEA (1ULL << 51)
#define SCR_TWERR (1ULL << 52)
#define SCR_PFAREN (1ULL << 53)
#define SCR_SRMASKEN (1ULL << 54)
#define SCR_ENIDCP128 (1ULL << 55)
#define SCR_DSE (1ULL << 57)
#define SCR_ENDSE (1ULL << 58)
#define SCR_FGTEN2 (1ULL << 59)
#define SCR_HDBSSEN (1ULL << 60)
#define SCR_HACDBSEN (1ULL << 61)
#define SCR_NSE (1ULL << 62)
/* GCSCR_ELx fields */