In GLib, GByteArray is an object managed by the library. Currently,
migrating a GByteArray requires treating it as a raw C struct and using
VMSTATE_VBUFFER_ALLOC_UINT32. For example, see vmstate_vdba in
ui/vdagent.c
QEMU cannot pretend that GByteArray is a C struct and simply use
VMS_ALLOC to g_malloc() the buffer. This is because, VMS_ALLOC blindly
overwrites the data pointer with a newly allocated buffer, thereby
leaking the previous memory. Besides, GLib tracks the array's capacity
in a hidden alloc field. Bypassing GLib APIs leave this capacity out of
sync with the newly allocated buffer, potentially leading to heap buffer
overflows during subsequent g_byte_array_append() calls.
This commit introduces VMSTATE_GBYTEARRAY which uses specific library
API calls (g_byte_array_set_size()) to safely resize and populate the
buffer.
Signed-off-by: Arun Menon <armenon@redhat.com>
Suggested-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260423105733.113046-2-armenon@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
A dummy DDR controller for ZYNQ has been added. While all registers are present,
not all are functional. Read and write access is validated, and the user mode
can be set. This provides a basic DDR controller initialization, preventing
system hangs due to endless polling or similar issues.
Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
Message-id: 20260518073401.11279-7-corvin.koehne@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
aspeed queue:
* Fix AST2600 RNG register definitions
* Add a USB EHCI functional test to the AST2600 SDK machine test
* Add a new anacapa-bmc machine (Meta/Facebook AST2600)
* Refactor SRAM to support AST1040 memory layout
* Add a new AST1040 Bridge IC SoC model and EVB machine
* Convert all Aspeed device models to use the Resettable
interface
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# gpg: Signature made Tue 26 May 2026 04:14:49 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20260526' of https://github.com/legoater/qemu: (37 commits)
hw/i2c/aspeed_i2c: convert to use Resettable interface
hw/adc/aspeed_adc: convert to use Resettable interface
hw/rtc/aspeed_rtc: convert to use Resettable interface
hw/fsi/aspeed_apb2opb: convert to use Resettable interface
hw/net/ftgmac100: convert to use Resettable interface
hw/watchdog/wdt_aspeed: convert to use Resettable interface
hw/i3c/aspeed_i3c: convert to use Resettable interface
hw/intc/aspeed_intc: convert to use Resettable interface
hw/intc/aspeed_vic: convert to use Resettable interface
hw/ssi/aspeed_smc: convert to use Resettable interface
hw/sd/aspeed_sdhci: convert to use Resettable interface
hw/gpio/aspeed_gpio: convert to use Resettable interface
hw/timer/aspeed_timer: convert to use Resettable interface
hw/pci-host/aspeed_pcie: convert to use Resettable interface
hw/misc/aspeed_ltpi: convert to use Resettable interface
hw/misc/aspeed_scu: convert to use Resettable interface
hw/misc/aspeed_sdmc: convert to use Resettable interface
hw/misc/aspeed_lpc: convert to use Resettable interface
hw/misc/aspeed_xdma: convert to use Resettable interface
hw/misc/aspeed_sbc: convert to use Resettable interface
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
The omap_dma device has support for modelling different variants
of the DMA block, as enumerated by the omap_dma_model enum:
3_0, 3_1 and 3_2. However, our one remaining OMAP SoC always
passes omap_dma_3_1 into the omap_dma_init() function, so the
handling for 3_0 and 3_2 is never used.
Remove the support for the other versions; this lets us
delete entirely two large functions that were specific
to 3.2 DMA to the LCD controller, and all their associated
fields in the omap_dma_lcd_channel_s struct.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260512203414.3633237-8-peter.maydell@linaro.org
The OMAP code creates a qemu_irq whose set function is
omap_mpu_wakeup(), and passes that irq into omap_mpuio_init(), which
saves it in its omap_mpuio_s::wakeup field. However nothing ever
touches that qemu_irq again, so omap_mpu_wakeup() is never called.
Remove all this as dead code. This lets us remove a direct call to
cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB) from within board/SoC code,
which is pretty ugly and might not even do the right thing these
days.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260512203414.3633237-7-peter.maydell@linaro.org
The omap1.c file includes some functions which used to be used by the
other OMAP SoC variants which we removed a while ago, but which we
missed when doing that removal. They have no callers, so we can
delete them.
This code was the last user of hw_error() in this file, so we
can also remove the hw-error.h include.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260512203414.3633237-3-peter.maydell@linaro.org
The omap1.c code has handling for an mpu_model field which is
an enum of which OMAP SoC model it is. We removed most of our
OMAP support some time ago, and now the only OMAP SoC we
implement is the OMAP310, which sets s->mpu_model = omap310
in omap310_mpu_init().
That makes all the handling for other settings of mpu_model dead
code; remove them. This includes the omap GPIO device's mpu_model
property which we set but which the device makes no use of, and the
omap-id-e20 memory region (because the OMAP310 satisfies
cpu_is_omap15xx(), so never executed the old if() block).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260512203414.3633237-2-peter.maydell@linaro.org
Some Aspeed SoCs contain multiple SRAM regions with different
sizes and MMIO mappings, such as internal SRAM and secure SRAM.
The current implementation models secure SRAM separately from the
generic SRAM representation, which complicates future multi-SRAM
support and expansion.
Increase ASPEED_SRAM_NUM to 2 and migrate secure SRAM to use the
common SRAM array representation. Rename the secure SRAM memmap
entry to ASPEED_DEV_SRAM1 and update AST10x0 to initialize both
SRAM regions through sram[] and sram_size[].
This unifies SRAM-like regions under a common representation and
prepares for future SoCs with additional SRAM regions.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Some Aspeed SoCs contain multiple SRAM regions with different
MMIO mappings, such as internal SRAM and secure SRAM.
Prepare for future multi-SRAM support by renaming the SRAM
memmap entry from ASPEED_DEV_SRAM to ASPEED_DEV_SRAM0.
This makes the numbering explicit and aligns with the
array-based SRAM representation introduced previously.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Prepare the Aspeed SoC model for future platforms that may contain
multiple SRAM regions with different sizes and MMIO mappings.
The current implementation stores SRAM size information in a single
sram_size field, which limits extensibility when additional SRAM
instances are introduced.
Convert sram_size into an array-based definition and update all
existing users to reference sram_size[0]. This aligns with the
previous SRAM MemoryRegion array conversion and provides a scalable
foundation for supporting multiple SRAM regions in future SoCs.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Several kinds of RAM are supported across Aspeed SoCs, including
SRAM, SDRAM, HyperRAM, secure SRAM, and generic SRAM. In addition,
different SoCs may expose multiple SRAM regions at different MMIO
addresses.
The current implementation models SRAM with a single MemoryRegion
instance, which makes future expansion cumbersome when additional
SRAM types or regions are introduced.
Prepare for future SoC designs by converting the SRAM MemoryRegion
from a single object into an array-based structure. This change
introduces ASPEED_SRAM_NUM and converts existing SRAM users to
reference sram[0].
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260525053036.3305181-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
QemuInputEvent now stores Linux key codes for key events. Use those
codes directly instead of translating between internal key code
representations.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-7-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
Add a text console helper that accepts Linux input key codes and use it
as the common implementation for qemu_text_console_put_qcode(). This lets
callers that already use Linux key codes avoid converting them back to
QKeyCode.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-6-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
Linux input key codes are a better internal representation than
QKeyCode:
- With Linux input key codes as the internal representation, keys
previously lost solely because the middle layer between event sources
and sinks used QKeyCode will be preserved, since Linux key codes
cover all keys that those sources and sinks use. For example,
KEY_KPJPCOMMA cannot be represented with QKeyCode, but it is widely
supported by event sources and sinks since it is included in linux,
atset1, atset2, usb, x11, osx, qnum (derived from atset1),
xorgxquartz, and xorgevdev (derived from linux).
- They make it possible to pass through Linux host key codes to Linux
guests to preserve all key inputs.
- They simplify consumers by avoiding QKeyCode aliases, namely
asterisk/kp_multiply and sysrq/print.
This matches the approach used by virtio and Xen.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-4-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
Since commit af07e5ff02 ("ui: convert key events to QKeyCodes
immediately"), all internal key events are expected to be represented as
QKeyCode. Replace KeyValue in QemuInputKeyEvent with QKeyCode to enforce
that and simplify key code retrieval.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-3-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
QAPI represents union members with wrapper structs and pointer
indirections. They are useful at the QMP boundary, but unnecessary for
QEMU's internal input events and make handlers more verbose.
Define QemuInputEvent as a plain internal tagged union and convert input
handlers, queues, and replay code to access payloads directly.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-2-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
Add QemuInputEvent as the input subsystem's name for InputEvent and use
it in input handler, queue, and replay interfaces.
This prepares for decoupling QEMU's internal input event representation
from the QAPI InputEvent type.
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260520-input-v3-1-7c9e4c7abe34@rsg.ci.i.u-tokyo.ac.jp>
RISC-V PR for 11.1.
* Remove spike as default machine
* Deprecate the shakti_c machine
* Set MISA.[C|X] based on the selected extensions
* Update Maintainers for OpenSBI Firmware
* Update OpenSBI to v1.8.1
* Avoid RISCVCPU copy in PMU FDT setup
* A collection of specification compliance improvements
* Fix Svnapot 64KB pages
* Handle source overlap of vector widening reduction instructions
* Check interrupt in SiFive UART after txctrl register is written
* Fix medeleg[11] read-only zero bit for M-mode ECALL
* Fix tail handling for vmv.s.x and vfmv.s.f
* Update the local AIA interrupt mask
* Add KVM support for Zicbop and BFloat16 extensions
* Fix the IOMMU FSC SV32 capability check
* Avoid caching PCI device IDs in the IOMMU
* Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
* Remove the internal CPU riscv_cpu_* arrays
* Fix IOCOUNTINH.CY toggle detection
* Fix the read of pmpaddr(0-63) CSRs
* Make hpmcounterh return the upper 32-bits
* Minor fixes and enhancements of RISC-V AIA devices
* Re-process IOMMU command queue after clearing CMD_ILL
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# gpg: Signature made Thu 21 May 2026 20:02:17 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu: (48 commits)
hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL
hw/intc: riscv_aplic: add trace events of APLIC read/write function
hw/intc: riscv_imsic: Add reset API to IMSIC
hw/intc: riscv_aplic: Add reset API to APLIC
hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
target/riscv: Make hpmcounterh return the upper 32-bits
hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping
target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs
hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection
target/riscv/cpu: remove riscv_cpu_* arrays
target/riscv/tcg: use isa_edata_arr[] to create user props
target/riscv: do not set defaults in cpu prop callback
target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
target/riscv/tcg: use isa_edata_arr[] to enable max exts
target/riscv/kvm: use isa_edata_arr[] for unavailable props
target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
target/riscv: remove riscv_cpu_named_features[]
target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Misc patches for iotests, qom, crypt & io
* Fix client side anoymous TLS credentials
* Fix return value semantics for qio_channel_flush
* Add ID validation of internal QOM constructor
* Fix ability to create internal QOM objects
without a parent
* Merge user creatable object constructor into
main QOM file
* Print reason for skipping I/O tests
* Remove redundant meson suits for I/O tests
* Add optional suites for many block drivers I/O tests
* Run I/O tests for 10 block drivers in GitLab CI
* Fix sudo check for LUKS I/O test
* Mark I/O test 151, 181, 185, 308 as flaky
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# gpg: Signature made Thu 21 May 2026 09:48:57 EDT
# gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full]
# gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full]
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu: (29 commits)
qom: drop user_creatable_add_type method
qom: allow object_new_with_prop* to trigger module loading
qom: fix ability to create objects without a parent
qom: add object_new_with_props_from_qdict
qom: move object_set_prop_keyval into object.c
qom: have object_set_props_keyval return bool
qom: shorten name of object_set_properties_from_keyval
qom: make errp last param in methods taking va_list
qom: validate ID format when creating objects
hw/vfio-user: use a valid object ID for iothread
qom: add trace events for object/property lifecycle
gitlab: remove I/O tests from build-tcg-disabled job
gitlab: add jobs for thorough block tests
iotests: mark 151, 181, 185 & 308 as flaky tests
iotests: fix check for sudo access in LUKS I/O test
iotests: validate dmsetup result in test 128
iotests: use 'driver' as collective term for either format or protocol
iotests: add nbd and luks to the I/O test suites
docs/devel/testing: expand documentation for 'make check-block'
iotests: add a meson suite / make target per block I/O tests format
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Allow target access to routines using the minmax flags.
Make the existing min/max wrappers inline.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Introduce a separate control from float_snan_rule
that applies only to the OCP E4M3 format.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Use bitfields to compress float_status from 18 bytes down to 8 bytes.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Move get_float_default_nan_pattern to softfloat-specialize.c.inc,
since there are no external users.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Drop FloatFTZDetection and use #defines, like we do for
tininess_before_rounding. Rename get_float_ftz_detection
to get_ftz_before_rounding and move to softfloat.c, as
there are no external users.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Rename get_float_detect_tininess to get_tininess_before_rounding
and move to softfloat.c, as there are no external users.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
We have, in the past, used any of uint8_t, uint16_t or int
to hold the set of exception flags. Use a typedef instead.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Now that we've exposed enough infrastructure, this can be
implemented in the backend that needs it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
