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Author SHA1 Message Date
Anton Johansson
9067113cdf target-info: Add target_riscv64() 
Adds a helper function to tell if the binary is targeting riscv64 or
not.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-7-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:50:37 +02:00
Anton Johansson
750d25fc66 configs/target: Implement per-binary TargetInfo structure for riscv 
Defines TargetInfo for 32- and 64-bit riscv binaries.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-6-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:50:37 +02:00
Philippe Mathieu-Daudé
599a673547 hw/riscv/spike: Use 'max' CPU type by default 
The Spike RISC-V ISA Simulator aims for maximum coverage,
so can start with the 'max' CPU type by default.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260526095731.63525-2-philmd@linaro.org>
 2026-05-27 08:50:37 +02:00
Anton Johansson
72b4174d2f hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries 
Register machines able to run in qemu-system-riscv32,
qemu-system-riscv64, or both.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-4-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:05:25 +02:00
Anton Johansson
90c356624a hw/core: Add riscv[32|64] to "none" machine 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-5-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:05:25 +02:00
Anton Johansson
40838c8251 hw/riscv: Add macros and globals for simplifying machine definitions 
Adds macros and global interfaces for defining machines available only
in qemu-system-riscv32, qemu-system-riscv64, or both.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-3-d1123ea63d9c@rev.ng>
[PMD: Constify InterfaceInfo]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:05:01 +02:00
Anton Johansson
a045f6a8e8 hw/riscv: Register generic riscv[32|64] QOM interfaces 
Defines generic 32- and 64-bit riscv machine interfaces for machines to
implement.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2026-05-27 08:03:27 +02:00
Stefan Hajnoczi
3f89b5de5b Merge tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu into staging 
target-arm queue:
 * hw/timer/mss_timer: Remove dead code in timer_write()
 * OMAP: Remove various pieces of dead code
 * target/arm: Set debug in attrs in translate_for_debug()
 * target/arm/ptw: Flip sense of get_phys_addr_* return values
 * tests/functional/aarch64: Bump up timeout on vbsa
 * target/arm: Fix minor FEAT_AFP corner case bugs
 * target/arm: Implement FEAT_FAMINMAX
 * target/arm: Implement FEAT_FPMR
 * target/arm: Some initial patches towards other FP8 features

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# gpg: Signature made Tue 26 May 2026 10:27:35 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20260526' of https://gitlab.com/pm215/qemu: (54 commits)
  target/arm: Move vectors_overlap to vec_internal.h
  target/arm: Split vector-type.h from cpu.h
  target/arm: Implement FSCALE for SME
  target/arm: Implement FSCALE for AdvSIMD
  target/arm: Add isar_feature_aa64_f8cvt
  target/arm: Implement ID_AA64FPFR0
  target/arm: Enable FEAT_FPMR for -cpu max
  linux-user/aarch64: Implement FPMR signal frames
  target/arm: Dump FPMR when present
  tests/functional/aarch64/rme: update images to support FEAT_FP8
  target/arm: Trap direct acceses to FPMR
  target/arm: Add FPMR_EL to TBFLAGS
  target/arm: Clear FPMR on ResetSVEState
  target/arm: Enable EnFPM bits for FEAT_FPMR
  target/arm: Update SCTLR bits for FEAT_FPMR
  target/arm: Introduce FPMR
  target/arm: Update HCRX bits for Arm ARM M.a.a
  target/arm: Update SCR bits for Arm ARM M.a.a
  target/arm: Enable FEAT_FAMINMAX for -cpu max
  target/arm: Implement FEAT_FAMINMAX for SVE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 13:20:15 -04:00
Stefan Hajnoczi
e28b83116a Merge tag 'pull-aspeed-20260526' of https://github.com/legoater/qemu into staging 
aspeed queue:

* Fix AST2600 RNG register definitions
* Add a USB EHCI functional test to the AST2600 SDK machine test
* Add a new anacapa-bmc machine (Meta/Facebook AST2600)
* Refactor SRAM to support AST1040 memory layout
* Add a new AST1040 Bridge IC SoC model and EVB machine
* Convert all Aspeed device models to use the Resettable
  interface

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# gpg: Signature made Tue 26 May 2026 04:14:49 EDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20260526' of https://github.com/legoater/qemu: (37 commits)
  hw/i2c/aspeed_i2c: convert to use Resettable interface
  hw/adc/aspeed_adc: convert to use Resettable interface
  hw/rtc/aspeed_rtc: convert to use Resettable interface
  hw/fsi/aspeed_apb2opb: convert to use Resettable interface
  hw/net/ftgmac100: convert to use Resettable interface
  hw/watchdog/wdt_aspeed: convert to use Resettable interface
  hw/i3c/aspeed_i3c: convert to use Resettable interface
  hw/intc/aspeed_intc: convert to use Resettable interface
  hw/intc/aspeed_vic: convert to use Resettable interface
  hw/ssi/aspeed_smc: convert to use Resettable interface
  hw/sd/aspeed_sdhci: convert to use Resettable interface
  hw/gpio/aspeed_gpio: convert to use Resettable interface
  hw/timer/aspeed_timer: convert to use Resettable interface
  hw/pci-host/aspeed_pcie: convert to use Resettable interface
  hw/misc/aspeed_ltpi: convert to use Resettable interface
  hw/misc/aspeed_scu: convert to use Resettable interface
  hw/misc/aspeed_sdmc: convert to use Resettable interface
  hw/misc/aspeed_lpc: convert to use Resettable interface
  hw/misc/aspeed_xdma: convert to use Resettable interface
  hw/misc/aspeed_sbc: convert to use Resettable interface
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 13:19:51 -04:00
Stefan Hajnoczi
3e233a3363 Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging 
Pull request

Denis Lunev's linux-aio stack exhaustion fix.

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# gpg: Signature made Mon 25 May 2026 11:18:07 EDT
# gpg:                using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate]
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
  block/linux-aio: bound ioq_submit() recursion depth

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 13:19:05 -04:00
Stefan Hajnoczi
f7d604e3cf Merge tag 'for-upstream2' of https://gitlab.com/bonzini/qemu into staging 
* lsi53c895a, apic, mc146818rtc: fix various bugs
* accel/mshv: implement cpu_thread_is_idle() hook
* json-parser: first patch from push parser conversion

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# gpg: Signature made Mon 25 May 2026 11:14:34 EDT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* tag 'for-upstream2' of https://gitlab.com/bonzini/qemu:
  json-parser: constify JSONToken
  mc146818rtc: Fix get_guest_rtc_ns() overflow bug
  accel/mshv: implement cpu_thread_is_idle() hook
  apic: fix delivery bitmask with modified xAPIC ids
  lsi53c895a: clear tag byte when processing messages
  lsi53c895a: fix use-after-free of cancelled request

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 13:18:52 -04:00
Stefan Hajnoczi
554cbfb1cf Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging 
UI pull request

- ui/input: Decouple internal and QAPI input events
- VNC OOB fixes
- vt100 fixes
- GTK focus fix

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# gpg: Signature made Mon 25 May 2026 02:27:04 EDT
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (38 commits)
  ui/gtk: Fix focus loss on re-attachment with single VC
  ui/input: Remove unused QKeyCode helpers and keymaps
  ui/console: Remove qemu_text_console_put_qcode()
  qemu-keymap: Use Linux key codes
  ui/vnc: Use Linux key codes
  ui/spice: Use Linux key codes
  ui/sdl2: Use Linux key codes
  ui/keymaps: Use Linux key codes
  ui/input-linux: Use Linux key codes
  ui/input-legacy: Use Linux key codes
  ui/input-barrier: Use Linux key codes
  ui/gtk: Use Linux key codes
  ui/dbus: Use Linux key codes
  ui/cocoa: Use Linux key codes
  replay: Use Linux key codes
  hw/m68k/next-kbd: Use Linux key codes
  hw/input/virtio-input: Use Linux key codes
  hw/input/ps2: Use Linux key codes
  hw/input/hid: Use Linux key codes
  hw/input/adb-kbd: Use Linux key codes
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2026-05-26 10:38:13 -04:00
Richard Henderson
1574211d1f target/arm: Move vectors_overlap to vec_internal.h 
We will shortly need this outside of sme_helper.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
784b01c77d target/arm: Split vector-type.h from cpu.h 
We want to be able to reference ARMVectorType etc from
common code, so move it out of cpu.h.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
d4c27fe91f target/arm: Implement FSCALE for SME 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
891388a9dd target/arm: Implement FSCALE for AdvSIMD 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
3b1ed6b5cf target/arm: Add isar_feature_aa64_f8cvt 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
2bdfbfe7f8 target/arm: Implement ID_AA64FPFR0 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
2430d49a17 target/arm: Enable FEAT_FPMR for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
82e6411eac linux-user/aarch64: Implement FPMR signal frames 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-17-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
5dd04faf9f target/arm: Dump FPMR when present 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Pierrick Bouvier
54cce8da06 tests/functional/aarch64/rme: update images to support FEAT_FP8 
As well, use -smp 1 since there is no visible speedup running with -smp 2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
13dbcfcc81 target/arm: Trap direct acceses to FPMR 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
cc04352a1f target/arm: Add FPMR_EL to TBFLAGS 
Prepare to perform access checks for direct and
indirect uses of FPMR.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
80e1cfc7ec target/arm: Clear FPMR on ResetSVEState 
FPMR is cleared when entering or exiting Streaming Mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
3a2ef816ee target/arm: Enable EnFPM bits for FEAT_FPMR 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
672f2ace5d target/arm: Update SCTLR bits for FEAT_FPMR 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
aa4d11f0f2 target/arm: Introduce FPMR 
Introduce the special register FPMR and its fields.
Migrate it when present.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
167a93306e target/arm: Update HCRX bits for Arm ARM M.a.a 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
394c4db5cf target/arm: Update SCR bits for Arm ARM M.a.a 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
697910f67f target/arm: Enable FEAT_FAMINMAX for -cpu max 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:41:00 +01:00
Richard Henderson
9972384eb3 target/arm: Implement FEAT_FAMINMAX for SVE 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260522220306.235200-5-richard.henderson@linaro.org
[PMM: add comments for TRANS_ macros]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:36:24 +01:00
Richard Henderson
1de033cf3e target/arm: Implement FEAT_FAMINMAX for SME 
Since there is no bfloat16 variant of FAMINMAX,
check for missing function pointer in do_z2z_nn_fpst.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:36:24 +01:00
Richard Henderson
dbbcf746c2 target/arm: Implement FEAT_FAMINMAX for AdvSIMD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260522220306.235200-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:36:24 +01:00
Richard Henderson
187304a617 target/arm: Implement ID_AA64ISAR3 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260522220306.235200-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2026-05-26 11:36:24 +01:00
Peter Maydell
23ece2805f target/arm: Set correct fp flags for FLOGB when FPCR.AH = 1 
Our implementation of the FLOGB insn does the operations entirely
in the helper function, without needing to use fpu functions.
This means it needs to handle all the fp status flags itself.
We aren't setting float_flag_input_denormal_used when we
use (i.e. do not flush to zero) an input denormal, which means
that FPCR.IDC isn't set when it should be for FPCR.AH=1.
We missed this when we added float_flag_input_denormal_used
and made the fpu/ code set it.

Add the missing float_raise().

Cc: qemu-stable@nongnu.org
Fixes: d38a57a3f ("target/arm: Enable FEAT_AFP for '-cpu max'")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260521122913.1565011-4-peter.maydell@linaro.org
 2026-05-26 10:19:27 +01:00
Peter Maydell
aa42300f86 target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs 
We should be using the F16-specific float_status for conversions from
half-precision, because halfprec inputs never set Input Denormal.  If
we use the FPST_A64 fpstatus then we will incorrectly set FPCR.IDC
for input-denormals when FPCR.AH=1.

In commit e07b48995a we updated most of the halfprec-to-other
conversion insns to use FPST_A64_F16 as part of implementing
FEAT_AHP.  However we missed the SVE FCVTLT instruction, which has a
halfprec-to-single encoding.

Correct the FPST we use for the hs variant of FCVTLT.

Cc: qemu-stable@nongnu.org
Fixes: e07b48995a ("target/arm: Use FPST_A64_F16 for halfprec-to-other conversions")a
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260521122913.1565011-3-peter.maydell@linaro.org
 2026-05-26 10:18:45 +01:00
Peter Maydell
446050c4df target/arm: SVE2 FMAXP, FMINP must honour AH=1 
The behaviour of floating-point maximum and minimum insns has
some odd special cases when FPCR.AH=1. We get this right in most
places (for instance, the ASIMD FMAXP, FMINP) but forgot about
it for the SVE2 versions of FMAXP and FMINP.

Cc: qemu-stable@nongnu.org
Fixes: 384433e709 ("target/arm: Implement FPCR.AH semantics for FMINP and FMAXP")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20260521122913.1565011-2-peter.maydell@linaro.org
 2026-05-26 10:18:45 +01:00
Peter Maydell
6122fffb1d tests/functional/aarch64: Bump up timeout on vbsa 
On a debug build, the virt_vbsa functional test takes about 2 minutes to
run on my machine, so it tends to time out. Bump the timeout to 4 mins.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20260518160440.1037245-1-peter.maydell@linaro.org
 2026-05-26 10:17:46 +01:00
Peter Maydell
36b3f32642 target/arm/ptw: Flip sense of get_phys_addr return value 
This completes the conversion of this family of functions to
returning true on success and false on failure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-15-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
24bf68e381 target/arm/ptw: Flip sense of get_phys_addr_for_at return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-14-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
66282b507e target/arm/ptw: Flip sense of arm_cpu_get_phys_addr return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-13-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
1567e559ff target/arm/ptw: Flip sense of get_phys_addr_gpc return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-12-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
df93432713 target/arm/ptw: Flip sense of get_phys_addr_nogpc return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-11-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
7d95f750fa target/arm/ptw: Flip sense of get_phys_addr_twostage return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-10-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
87d50e8049 target/arm/ptw: Flip sense of pmsav8_mpu_lookup return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-9-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
26f790fe37 target/arm/ptw: Flip sense of get_phys_addr_pmsav8 return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-8-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
6d22efc8aa target/arm/ptw: Flip sense of get_phys_addr_pmsav7 return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-7-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
6325e4bc20 target/arm/ptw: Flip sense of get_phys_addr_psmav5 return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-6-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00
Peter Maydell
9d62212fde target/arm/ptw: Flip sense of get_phys_addr_v5 return value 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260515142541.571911-5-peter.maydell@linaro.org
 2026-05-26 10:16:36 +01:00